Vertical field effect transistors with bottom contact metal directly beneath fins

1. A method for fabricating a vertical fin field-effect-transistor, the method comprising:

forming a structure comprising a substrate, a source/drain layer, and a plurality of fins formed on the first source/drain layer, wherein the source/drain layer comprises a first semiconductor layer, a sacrificial layer, and a second semiconductor layer;

forming a bottom spacer layer in contact with the second semiconductor layer and the plurality of fins;

forming a gate structure in contact with the plurality of fins and the bottom spacer layer;

depositing a dielectric layer in contact with at least the gate structure and the bottom spacer layer;

removing at least a portion of the dielectric layer adjacent to the gate structure and a portion of the second semiconductor, the removing forming a trench exposing a portion of the sacrificial layer;

after the trench has been formed, removing the sacrificial layer, wherein removal of the sacrificial layer forms a cavity between the first semiconductor layer and the second semiconductor layer adjacent to and under the gate structure; and

depositing a contact material within the trench and the cavity.

2. The method of claim 1 , wherein forming the structure comprises:

epitaxially growing the first semiconductor layer on and in contact with the substrate;

epitaxially growing the sacrificial layer on and in contact with the first semiconductor layer; and

epitaxially growing the second semiconductor layer on and in contact with the sacrificial layer.

3. The method of claim 1 , wherein forming the gate structure comprises:

forming a separate dielectric layer on and in contact with each fin in the plurality of fins; and

forming a gate layer in contact with each of the separate dielectric layers.

4. The method of claim 1 , further comprising:

forming a top spacer layer in contact with the gate structure and each fin in the plurality of fins.

5. The method of claim 4 , further comprising:

forming an additional source/drain layer on and in contact with the top spacer layer.

6. The method of claim 5 , further comprising:

removing at least a portion of the dielectric layer above to the gate structure, the removing forming a trench exposing a portion of the top spacer layer.

7. The method of claim 6 , further comprising:

depositing a contact material within the trench.

8. A vertical fin field-effect-transistor comprising at least:

a substrate;

a first source/drain layer comprising a first semiconductor layer and a second semiconductor layer;

a plurality of fins each formed on and in contact with the second semiconductor layer;

a gate structure in contact with the plurality of fins;

a second source/drain layer formed on the gate structure; and

a contact comprising a vertical portion formed adjacent to the gate structure and a horizontal portion formed between the first and second semiconductor layers and at least under the gate structure.

9. The vertical fin field-effect-transistor of claim 8 , further comprising:

a bottom spacer layer in contact with the second semiconductor layers and the plurality of fins.

10. The vertical fin field-effect-transistor of claim 8 , further comprising:

a top spacer layer in contact with the gate structure and the plurality of fins.

11. The vertical fin field-effect-transistor of claim 10 , wherein the second source/drain layer is formed on and in contact with the top spacer layer and the plurality of fins.

12. The vertical fin field-effect-transistor of claim 8 , wherein the gate structure comprises:

separate dielectric layers in contact with each fin in the plurality of fins; and

a gate layer in contact with each of the separate dielectric layers.

13. The vertical fin field-effect-transistor of claim 8 , further comprising:

a contact formed in contact with at least a portion of the second source/drain layer.

14. The vertical fin field-effect-transistor of claim 8 , wherein each fin in the plurality of fins comprises a first doped region and a second doped region.

15. An integrated circuit comprising:

at least one vertical fin field-effect-transistor comprising at least:

a substrate;

a first source/drain layer comprising a first semiconductor layer and a second semiconductor layer;

a plurality of fins each formed on and in contact with the second semiconductor layer;

a gate structure in contact with the plurality of fins;

a second source/drain layer formed on the gate structure; and

a contact comprising a vertical portion formed adjacent to the gate structure and a horizontal portion formed between the first and second semiconductor layers and at least under the gate structure.

16. The integrated circuit of claim 15 , wherein the vertical fin field-effect-transistor further comprises:

a bottom spacer layer in contact with the second semiconductor layers and the plurality of fins.

17. The integrated circuit of claim 15 , wherein the vertical fin field-effect-transistor further comprises:

a top spacer layer in contact with the gate structure and the plurality of fins.

18. The integrated circuit of claim 17 , wherein the second source/drain layer is formed on and in contact with the top spacer layer and the plurality of fins.

19. The integrated circuit of claim 15 , wherein the gate structure comprises:

separate dielectric layers in contact with each fin in the plurality of fins; and

a gate layer in contact with each of the separate dielectric layers.

20. The integrated circuit of claim 15 , wherein the vertical fin field-effect-transistor further comprises:

a contact formed in contact with at least a portion of the second source/drain layer.