III-V compound semiconductor channel material formation on mandrel after middle-of-the-line dielectric formation

1. A method of forming a semiconductor structure, said method comprising:

providing, in an NFET device region, at least one sacrificial gate structure straddling over a portion of at least semiconductor material portion;

forming a source/drain structure from exposed sidewalls of each semiconductor material portion;

removing said at least one semiconductor material portion not protected by said at least one sacrificial gate structure, while maintaining at least a semiconductor mandrel beneath each sacrificial gate structure, each semiconductor mandrel comprises a remaining portion of said semiconductor material portion;

forming a middle-of-the-line (MOL) dielectric material laterally surrounding each sacrificial gate structure and atop each source/drain structure, wherein said MOL dielectric material has a topmost surface that is coplanar with each sacrificial gate structure;

removing each sacrificial gate structure to provide a cavity, said cavity exposing at least one sidewall of each semiconductor mandrel;

forming a III-V compound semiconductor channel material from said at least one sidewall of each semiconductor mandrel;

removing each semiconductor mandrel to provide a gate cavity; and

forming a functional gate structure in each gate cavity.

2. The method of claim 1 , wherein said forming said source/drain structure comprises a selective epitaxial growth process.

3. The method of claim 1 , wherein said source/drain structure comprises a semiconductor material containing an n-type dopant.

4. The method of claim 1 , further comprising forming at least one PFET device in a PFET device region that lies to a periphery of said NFET device region, said forming said PFET device is performed prior to forming said source/drain structure.

5. The method of claim 4 , wherein said forming said PFET device region comprising:

forming a dielectric material layer on said NFET device region and said PFET device region; and

forming said PFET device utilizing a replacement gate process; and

removing said dielectric material layer from said NFET device region.

6. The method of claim 1 , wherein said removing said semiconductor material portion not protected by said at least one sacrificial gate structure comprises at least one anisotropic etch.

7. The method of claim 1 , wherein each semiconductor material portion is a lower layer of a patterned material stack, said patterned material stack further comprises a hard mask located on each semiconductor material portion, and wherein said hard mask not protected by said at least one sacrificial gate structure is removed during said removing said at least one semiconductor material portion not protected by said at least one sacrificial gate structure.

8. The method of claim 1 , wherein said forming said III-V compound semiconductor channel material comprises a selective epitaxial growth process.

9. The method of claim 1 , wherein each semiconductor mandrel comprises Si, and said at least one sidewall of each semiconductor mandrel has a (111) crystal orientation.

10. The method of claim 1 , wherein said removing each semiconductor mandrel comprises at least one anisotropic etch.

11. The method of claim 1 , wherein each III-V compound semiconductor channel material further comprises a p-type.

12. The method of claim 1 , wherein each III-V compound semiconductor channel material has a topmost surface and a bottommost surface that are coplanar with a topmost surface and a bottommost surface, respectively, of each source/drain structure.

13. The method of claim 1 , wherein said functional gate structure has a topmost surface that is coplanar with a topmost surface of said MOL dielectric material.

14. The method of claim 13 , wherein said functional gate structure comprises a U-shaped gate dielectric portion.

15. The method of claim 1 , wherein each III-V compound semiconductor channel material has a width from 2 nm to 20 nm and a height from 10 nm to 100 nm.

16. The method of claim 1 , further comprising a substrate located beneath said at least one sacrificial gate structure and said at least one semiconductor material portion.

17. The method of claim 16 , wherein said substrate is an insulator layer or a remaining portion of a bulk semiconductor substrate.

18. The method of claim 1 , wherein each semiconductor material portion is formed by:

providing a material stack, of from bottom to top, a semiconductor material layer and a hard mask layer; and

patterning said material stack.

19. The method of claim 1 , wherein each sacrificial gate structure lies perpendicular to each semiconductor material portion.

20. The method of claim 1 , wherein said removing each sacrificial gate structure comprises one or more anisotropic etching processes.