Approach to fabrication of an on-chip resistor with a field effect transistor
A method of forming a resistor adjacent to a fin field effect transistor on a substrate, including, forming a plurality of vertical fins on the substrate, forming a dielectric fill layer on the plurality of vertical fins, forming at least two dummy gate structures on the plurality of vertical fins, forming a replaceable resistor structure on the dielectric fill layer over a region of the substrate unoccupied by vertical fins, forming a sidewall spacer on the at least two dummy gate structures and the replaceable resistor structure, removing the replaceable resistor structure to form a trench, and forming a resistor structure in the trench.
1. A resistor on a substrate, comprising:
a dielectric fill layer on the substrate;
an interlayer dielectric (ILD) layer on the dielectric fill layer;
a sidewall spacer on a sidewall of the ILD layer and on the dielectric fill layer;
a pinch-off layer on the sidewall spacer;
a resistor layer on the pinch-off layer; and
an insulating fill layer on the resistor layer.
2. The resistor of claim 1 , wherein the pinch-off layer has a thickness in the range of about 5 nm to about 30 nm.
3. The resistor of claim 1 , wherein the resistor layer has a thickness in the range of about 5 nm to about 30 nm.
4. The resistor of claim 3 , wherein the resistor layer is U-shaped.
5. The resistor of claim 3 , further comprising two electrical contacts on opposite ends of the U-shaped resistor layer.
6. The resistor of claim 3 , wherein the resistor layer is tungsten silicide (WSi), tungsten (W), titanium nitride (TiN), or combinations thereof.
7. The resistor of claim 3 , wherein the insulating fill layer is selected from the group consisting of silicon nitride (SiN), silicon oxynitride (SiON), and silicon oxycarbide (SiOC).
8. A resistor adjacent to a fin field effect transistor on a substrate, comprising:
a plurality of vertical fins on the substrate;
a gate structure on the plurality of vertical fins to form the fin field effect transistor;
a sidewall spacer on a region of the substrate adjacent to the vertical fins;
a pinch-off layer on the sidewall spacer;
a resistor layer on the pinch-off layer; and
an insulating fill layer on the resistor layer.
9. The resistor adjacent to a fin field effect transistor of claim 8 , wherein the sidewall spacer is silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon borocarbide (SiBC), silicon boro carbonitride (SiBCN), boron carbide (BC), boron nitride (BN), or combinations thereof.
10. The resistor adjacent to a fin field effect transistor of claim 8 , wherein the sidewall spacer and pinch-off layer are at least partially on a dielectric fill layer.
11. The resistor adjacent to a fin field effect transistor of claim 8 , wherein the resistor layer has a thickness in a range of about 10 nm to about 20 nm.
12. The resistor adjacent to a fin field effect transistor of claim 11 , wherein the resistor layer is tungsten silicide (WSi), tungsten (W), titanium nitride (TiN), or combinations thereof.
13. The resistor adjacent to a fin field effect transistor of claim 11 , further comprising an electrical contact on each of an opposite end of the resistor layer.
14. An on-chip resistor adjacent to a fin field effect transistor on a semiconductor substrate, comprising:
a plurality of vertical fins on the semiconductor substrate;
a gate structure on the plurality of vertical fins to foi in the fin field effect transistor;
a sidewall spacer on a region of the substrate adjacent to the vertical fins;
a pinch-off layer on the sidewall spacer;
a resistor layer on the pinch-off layer, wherein the resistor layer is tungsten silicide (WSi), tungsten (W), titanium nitride (TiN), or combinations thereof; and
an insulating fill layer on the resistor layer.
15. The on-chip resistor adjacent to a fin field effect transistor of claim 14 , wherein each of the plurality of vertical fins have a height in the range of about 20 nm to about 40 nm.
16. The on-chip resistor adjacent to a fin field effect transistor of claim 14 , wherein the sidewall spacer has a thickness in the range of about 4 nm to about 8 nm.
17. The on-chip resistor adjacent to a fin field effect transistor of claim 14 , wherein the resistor layer has a thickness in the range of about 5 nm to about 30 nm, and is U-shaped.
18. The on-chip resistor adjacent to a fin field effect transistor of claim 17 , further comprising electrical contacts on opposite ends of the resistor layer configured to allow an electrical current to flow from a first electrical contact to a second electrical contact through the resistor layer.
19. The on-chip resistor adjacent to a fin field effect transistor of claim 18 , wherein the insulating fill layer is selected from the group consisting of silicon nitride (SiN), silicon oxynitride (SiON), and silicon oxycarbide (SiOC).
20. The on-chip resistor adjacent to a fin field effect transistor of claim 19 , wherein the pinch-off layer is on the dielectric fill layer.