Vertical finfet with strained channel
A vertical transistor including a strained vertical semiconductor material channel pillar and a method of forming the same are provided. A strained vertical semiconductor materials pillar is first formed and is used to provide the strained vertical semiconductor material channel pillar of the vertical transistor of the present application. The strained vertical semiconductor material pillar is always mechanically anchored during various vertical transistor processing steps so that in the final structure strain is preserved.
1. A semiconductor structure comprising:
a strained semiconductor material channel pillar located above a substrate;
a first functional gate structure located on a first sidewall of said strained semiconductor material channel pillar;
a second functional gate structure located on a second sidewall surface of said strained semiconductor material channel pillar;
a first source/drain structure in contact with a bottommost surface of said strained semiconductor material channel pillar and extending beneath said first and second functional gate structures;
a second source/drain structure in contact with a topmost surface of said strained semiconductor material channel pillar and extending above said first and second functional gate structures; and
a bottom spacer located between a bottommost surface of each of said first and second functional gate structures and a portion of said first source/drain structure.
2. The semiconductor structure of claim 1 , further comprising a top spacer located between a topmost surface of each of said first and second functional gate structures and a portion of said second source/drain structure.
3. The semiconductor structure of claim 1 , wherein
said first source/drain structure comprises:
a first doped semiconductor extension region having a topmost surface in direct physical contact with said bottommost surface of said strained semiconductor material channel pillar, and
first epitaxial doped semiconductor structures extending from sidewalls of said first doped semiconductor extension region; and
said second source/drain structure comprises:
a second doped semiconductor extension region having a bottommost surface in direct physical contact with said topmost surface of said strained semiconductor material channel pillar, and
second epitaxial doped semiconductor structures extending from sidewalls of said second doped semiconductor extension region.
4. The semiconductor structure of claim 1 , wherein said substrate is an insulator layer, and wherein a bottommost surface of said first source/drain structure is in direct physical contact with a topmost surface of said insulator layer.
5. The semiconductor structure of claim 1 , wherein said strained semiconductor material channel pillar comprises tensily strained silicon, compressively strained germanium, a compressively strained silicon germanium alloy, or a tensily strained III-V compound semiconductor.
6. The semiconductor structure of claim 1 , wherein said first and second functional gate structures comprise a same gate dielectric material and a same gate conductor material.
7. The semiconductor structure of claim 6 , wherein said first and second functional gate structures have a same height.
8. The semiconductor structure of claim 6 , wherein said first and second functional gate structures contain a gate dielectric portion having a topmost surface that extends above a topmost surface of a gate conductor structure.
9. The semiconductor structure of claim 1 , wherein said first and second functional gate structures comprise at least one of a different gate dielectric material or a different gate conductor material.
10. The semiconductor structure of claim 9 , wherein said first and second functional gate structures contain a gate dielectric portion having a topmost surface that extends above a topmost surface of a gate conductor structure.
11. The semiconductor structure of claim 9 , wherein said first and second functional gate structures have different heights.
12. A method of forming a semiconductor structure, said method comprising:
forming at least one silicon germanium mandrel structure on a surface of a substrate, wherein said at least one silicon germanium mandrel structure is strained;
forming a strained semiconductor material pillar on opposing sidewalls of said at least one silicon germanium mandrel structure;
forming, with said at least one silicon germanium mandrel structure present, a first portion of a first source/drain structure;
forming a first functional gate structure on one side of each strained semiconductor material pillar;
removing said at least one silicon germanium mandrel structure with said first functional gate stack in place to maintain the strain of each of said strained semiconductor material pillars;
forming, on another side of each of said strained semiconductor material pillars, a second portion of said first source/drain structure and a second functional gate structure; and
forming a second source/drain structure located above said first and second functional gate structures and in contact with a topmost surface of each of said strained semiconductor material pillars.
13. The method of claim 12 , wherein said forming said at least one silicon germanium mandrel structure on said surface of said substrate comprises:
epitaxially growing a silicon germanium alloy layer on a surface of a silicon layer;
converting said silicon germanium alloy layer and said silicon layer into a strained silicon germanium alloy layer; and
patterning said strained silicon germanium alloy layer.
14. The method of claim 12 , wherein said forming said strained semiconductor material pillar comprises a lateral epitaxially growth process.
15. The method of claim 12 , wherein
said first source/drain structure comprises:
a first doped semiconductor extension region having a topmost surface in direct physical contact with said bottommost surface of said strained semiconductor material pillar, and
first epitaxial doped semiconductor structures extending from sidewalls of said first doped semiconductor extension region; and
said second source/drain structure comprises:
a second doped semiconductor extension region having a bottommost surface in direct physical contact with said topmost surface of said strained semiconductor material pillar, and
second epitaxial doped semiconductor structures extending from sidewalls of said second doped semiconductor extension region.
16. The method of claim 12 , wherein said first and second functional gate structures comprise a same gate dielectric material and a same gate conductor material.
17. The method of claim 12 , wherein said first and second functional gate structures comprise at least one of a different gate dielectric material or a different gate conductor material.
18. The method of claim 12 , further comprising forming a bottom spacer below said first and second functional gate structures, and forming a top spacer above said first and second functional gate structures.
19. The method of claim 12 , forming comprising forming a bottom spacer below said first and second functional gate structures, and a top spacer above only said first functional gate structure.