Sidewall spacer with controlled geometry
Embodiments herein describe techniques for forming sidewalls on vertical structures on a semiconductor substrate. In one embodiment, the semiconductor substrate includes a first layer (e.g., a conductive layer such as an electrode) on which a second layer (e.g., an insulator) is disposed. An undercut etch is performed which selectively etches the sides of the material in the first layer but not the material in the second layer. A conformal deposition process is used to deposit the material of the sidewall into the undercut regions. Further etches can be performed to shape the sidewalls disposed on the sides of the material in the first layer.
1. A method, comprising:
providing a first layer directly contacting a first side of a second layer and a substrate directly contacting a second side of the second layer, wherein the first side is opposite the second side, and wherein a material in the first layer is different than a material in the second layer;
selectively etching the material of the second layer to form an undercut region in the second layer, wherein the material of the first layer and the substrate are not removed when etching the second layer;
filling the undercut region with an insulative material using a conformal deposition process;
etching the insulative material thereby exposing a top portion of the first layer and a portion of the substrate to form at least one sidewall spacer in the second layer, wherein the at least one sidewall spacer includes the undercut region;
after exposing the top portion of the first layer and the portion of the substrate, forming at least one via extending through the first layer; and
depositing a conductive material into the via, wherein the conductive material electrically connects the second layer to a conductive layer disposed above the first layer.
2. The method of claim 1 , wherein the material of the first layer comprises an insulator and a material of the second layer comprises a conductor.
3. The method of claim 1 , wherein the conformal deposition process is an atomic layer deposition (ALD) process comprising a plurality of precursors used to form the insulative material.
4. The method of claim 1 , wherein selectively etching the material of the second layer comprises:
performing an isotropic etch on the material of the second layer, wherein the isotropic etch etches the material of the second layer in a first direction and in a second direction perpendicular to the first direction.
5. The method of claim 4 , wherein the isotropic etch is performed using a reactive ion etch (RIE).
6. The method of claim 1 , wherein filling the undercut region with the insulative material comprises:
controlling the conformal deposition process such that a thickness of the insulative material is substantially equal to one half of a width of the undercut region.
7. The method of claim 1 , wherein etching the insulative material to form the at least one sidewall spacer comprises:
performing RIE to remove at least a portion of the insulative material.
8. The method of claim 7 , wherein, after performing RIE, a height of the least one sidewall spacer is equal to a height of the second layer.
9. A method, comprising:
providing a dielectric layer directly contacting a first side of a conductor and a substrate directly contacting a second side of the conductor, wherein the first side is opposite the second side;
selectively etching the conductor to form an undercut region, wherein the material of the dielectric layer and the substrate are not removed when etching the conductor;
filling the undercut region with a first material using a conformal deposition process;
etching the first material thereby exposing a top portion of the dielectric layer and a portion of the substrate to form at least one sidewall spacer contacting the conductor, wherein the at least one sidewall spacer includes the undercut region;
after exposing the top portion of the dielectric layer and the portion of the substrate, forming at least one via extending through the dielectric layer; and
depositing a conductive material into the via, wherein the conductive material electrically connects the conductor to a conductive layer disposed above the first layer.
10. The method of claim 9 , wherein the conformal deposition process is an ALD process comprising a plurality of precursors used to form the first material.
11. The method of claim 10 , wherein the first material comprises an oxide.
12. The method of claim 9 , wherein selectively etching the conductor comprises:
performing an isotropic etch on the conductor, wherein the isotropic etch etches the conductor in a first direction and in a second direction perpendicular to the first direction.
13. The method of claim 12 , wherein the isotropic etch is performed using a RIE.
14. The method of claim 9 , wherein filling the undercut region with the first material comprises:
controlling the conformal deposition process such that a thickness of the first material is substantially equal to one half of a width of the undercut region.
15. The method of claim 9 , wherein etching the first material to form the at least one sidewall spacer comprises:
performing a RIE to remove at least a portion of the first material.
16. The method of claim 15 , wherein, after performing the RIE, a height of the least one sidewall spacer is equal to a height of the conductor.
17. A method, comprising:
providing a first layer directly contacting a first side of a second layer and a substrate directly contacting a second side of the second layer, wherein the first side is opposite the second side, and wherein a material in the first layer is different than a material in the second layer;
selectively etching the material of the second layer, but not the material of the first layer and the substrate, wherein the material of the first layer and the substrate are not removed when etching the second layer, to form respective undercut regions on third and fourth sides of the material in the second layer;
filling the respective undercut regions with an oxide material using a conformal deposition process;
etching the oxide material thereby exposing a top portion of the first layer and a portions of the substrate to form two sidewall spacers in the second layer, wherein the two sidewall spacers include the respective undercut regions;
after exposing the top portion of the first layer and the portions of the substrate, forming at least one via extending through the first layer; and
depositing a conductive material into the via, wherein the conductive material electrically connects the second layer to a conductive layer disposed above the first layer.
18. The method of claim 17 , wherein the two sidewall spacers directly contact the third and fourth sides of the material in the second layer.