Techniques for forming finFET transistors with same fin pitch and different source/drain epitaxy configurations

1. A method of forming a fin field-effect transistor (finFET) device, comprising:

partially forming fins in a substrate, wherein at least one of the fins is formed in a first region of the substrate, and at least another one of the fins is formed in a second region of the substrate;

selectively forming spacers on opposite sides of only the fins in the second region of the substrate;

completing formation of the fins such that the fins in the first region of the substrate have a uniform width and, based on the spacers, the fins in the second region of the substrate have a base that is wider than the fins in the first region of the substrate;

depositing an insulator between the fins;

recessing the insulator to expose top portions of the fins;

forming at least one gate over a region of the fins that serves as a channel region of the finFET device, and wherein regions of the fins extending out from under the gate serve as source and drain regions of the finFET device;

further recessing the insulator in the source and drain regions to expose bottom portions of the fins, wherein the bottom portions of the fins exposed in the source and drain regions have a different width in the first region of the substrate versus the second region of the substrate, with the base of the fins in the second region of the substrate that are wider than the fins in the first region of the substrate protruding from the insulator; and

growing an epitaxial material in the source and drain regions that is un-merged in the first region of the substrate yet is merged in the second region of the substrate due to the base of the fins in the second region of the substrate being wider than the fins in the first region of the substrate and protruding from the insulator.

2. The method of claim 1 , wherein the fins have a uniform pitch x.

3. The method of claim 1 , wherein the fins in the first region of the substrate have a straight sidewall profile.

4. The method of claim 1 , wherein the fins in the second region of the substrate have a stepped profile.

5. The method of claim 1 , wherein the top portions of the fins in the second region of the substrate each have a width w, and the bottom portions of the fins in the second region of the substrate each have a width w′, wherein w′>w.

6. The method of claim 5 , wherein the top portions and the bottom portions of the fins in the first region of the substrate each have the width w.

7. The method of claim 1 , further comprising:

forming the spacers on opposite sides of the fins;

forming a mask covering the spacers and fins in only the second region of the substrate;

removing the spacers from the fins in the first region of the substrate; and

removing the mask.

8. The method of claim 1 , wherein the spacers comprise oxide spacers.

9. The method of claim 1 , wherein the spacers comprise nitride spacers.

10. The method of claim 1 , further comprising:

forming gate spacers on opposite sides of the gate.

11. The method of claim 10 , further comprising:

depositing a gate spacer material onto the substrate and alongside the gate; and

removing the gate spacer material from the fins in the source and drain regions.

12. The method of claim 11 , wherein the gate spacer material comprises a nitride material.

13. The method of claim 12 , wherein the nitride material comprises silicon nitride (SiN).

14. The method of claim 11 , wherein the insulator is further recessed during removal of the gate spacer material from the fins.

15. The method of claim 1 , wherein the insulator comprises an oxide material.

16. The method of claim 15 , wherein the insulator comprises a shallow trench isolation (STI) oxide.

17. The method of claim 16 , wherein the STI oxide comprises silicon dioxide (SiO 2 ).

18. The method of claim 1 , wherein the substrate comprises a bulk substrate.

19. The method of claim 18 , wherein the bulk substrate is selected from the group consisting of: a bulk silicon (Si) substrate, a bulk germanium (Ge) substrate, and a bulk silicon-germanium (SiGe) substrate.

20. The method of claim 1 , wherein the gate comprises a gate line that covers both the fins in the first region of the substrate and the fins in the second region of the substrate.