IP Library Granted Patent US 9,972,540
Granted Patent B2
US 9,972,540 · App. 15/230,443 · Granted May 15, 2018

Semiconductor device having multiple thickness oxides

Inventors: Qing Cao (Yorktown Heights, NY); Kangguo Cheng (Schenectady, NY); Zhengwen Li (Chicago, IL); Fei Liu (Yorktown Heights, NY)
Assignee: International Business Machines Corporation
H01L21/823462H01L21/0214H01L21/02247H01L21/02252H01L21/823857H01L27/088H01L29/518H01L29/66545H01L21/28088H01L21/28238H01L29/517
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Quick Facts
Patent No.
US 9,972,540
App. No.
15/230,443
Granted
May 15, 2018
Kind
B2
Abstract

Method for fabricating semiconductor device comprising: forming a dummy gate on a first nitrided oxide layer and a non-nitrided oxide layer; nitridizing an exposed section of the non-nitrided oxide layer to form a second nitrided oxide layer; forming an interlayer dielectric on the first nitrided oxide layer and the second nitrided oxide layer; removing the dummy gate from the first nitrided oxide layer to form a first opening with the first nitrided oxide layer exposed in the first opening; removing the dummy gate from the non-nitrided oxide layer to form a second opening with a non-nitrided portion of oxide layer exposed in the second opening; removing the non-nitrided portion of the oxide layer; forming a first dielectric layer and first metal gate material in the first opening; and forming a second dielectric layer and second metal gate material in the second opening.

Claims (46)

1. Method for fabricating semiconductor device comprising:

forming an oxide layer on a semiconductor substrate;

nitridizing a first portion of the oxide layer to form a first nitrided oxide layer;

forming a dummy gate on the first nitrided oxide layer and on a second portion of the oxide layer;

nitridizing an exposed section of the second portion of the oxide layer not covered by the dummy gate on the second portion of the oxide layer to form a second nitrided oxide layer;

forming an interlayer dielectric on the first nitrided oxide layer and on the second nitrided oxide layer;

removing the dummy gate from the first nitrided oxide layer to form a first opening with the first nitrided oxide layer exposed in the first opening;

removing the dummy gate from the second portion of the oxide layer to form a second opening with a non-nitrided section of the second portion of the oxide layer exposed in the second opening;

removing the non-nitrided section of the second portion of the oxide layer;

forming a first dielectric layer in the first opening and filling a remainder of the first opening with a first metal gate material; and

forming a second dielectric layer in the second opening and filling a remainder of the second opening with a second metal gate material.

2. The method of claim 1 further comprising forming spacers on the first nitrided oxide layer, forming a source and a drain in the semiconductor substrate underneath the first nitrided oxide layer, forming spacers on the second nitrided oxide layer and forming a source and a drain in the semiconductor substrate underneath the second nitrided oxide layer.

3. The method of claim 1 wherein the first dielectric layer is in contact with the first nitrided oxide layer and the second dielectric layer is in contact with the semiconductor substrate.

4. The method of claim 3 wherein the first nitrided oxide layer in contact with the first dielectric layer and the first dielectric layer together have a first thickness and the second dielectric layer in contact with the semiconductor substrate has a second thickness such that the first thickness is greater than the second thickness.

5. The method of claim 1 wherein nitridizing the first portion of the oxide layer further includes protecting the second portion of the oxide layer during the nitridizing from being nitrided.

6. The method of claim 1 wherein nitridizing the first portion of the oxide layer is by a nitrogen plasma process.

7. The method of claim 1 wherein nitridizing the exposed section of the second portion of the oxide layer is by a nitrogen plasma process.

8. The method of claim 1 wherein removing the non-nitrided section of the second portion of the oxide layer further includes protecting the first nitrided oxide layer during the removing.

9. The method of claim 1 wherein the first dielectric layer and the second dielectric layer are continuous on sides and a bottom of the first opening and the second opening, respectively.

10. Method for fabricating semiconductor device comprising:

forming an oxide layer on a semiconductor substrate;

nitridizing a first portion of the oxide layer to form a first nitrided oxide layer while simultaneously protecting a second portion of the oxide layer during the nitridizing from being nitrided;

forming a dummy gate on the first nitrided oxide layer and the second portion of the oxide layer;

nitridizing an exposed section of the second portion of the oxide layer not covered by the dummy gate on the second portion of the oxide layer to form a second nitrided oxide layer;

forming spacers on the first nitrided oxide layer adjacent to the dummy gate on the first nitrided oxide layer;

forming spacers on the second nitrided oxide layer adjacent to the dummy gate on the second portion of the oxide layer;

forming an interlayer dielectric on the first nitrided oxide layer and the second nitrided oxide layer;

removing the dummy gate from the first nitrided oxide layer to form a first opening with the first nitrided oxide layer exposed in the first opening;

removing the dummy gate from the second portion of the oxide layer to form a second opening with a non-nitrided section of the second portion of the oxide layer exposed in the second opening;

removing the non-nitrided section of the second portion of the oxide layer;

forming a first dielectric layer in the first opening and filling a remainder of the first opening with a first metal gate material; and

forming a second dielectric layer in the second opening and filling a remainder of the second opening with a second metal gate material.

11. The method of claim 10 further comprising forming a source and a drain in the semiconductor substrate underneath the first nitrided oxide layer and forming a source and a drain in the semiconductor substrate underneath the second nitrided oxide layer.

12. The method of claim 1 wherein the first dielectric layer is in contact with the first nitrided oxide layer and the second dielectric layer is in contact with the semiconductor substrate such that there is not a nitrided oxide layer between the second dielectric layer and the semiconductor substrate.

13. The method of claim 12 wherein the first nitrided oxide layer in contact with the first dielectric layer and the first dielectric layer together have a first thickness and the second dielectric layer in contact with the semiconductor substrate has a second thickness such that the first thickness is greater than the second thickness.

14. The method of claim 10 wherein nitridizing the first portion of the oxide layer is by a nitrogen plasma process.

15. The method of claim 10 wherein nitridizing the exposed section of the second portion of the oxide layer is by a nitrogen plasma process.

16. The method of claim 10 wherein removing the non-nitrided section of the second portion of the oxide layer further includes protecting the first nitrided oxide layer during the removing.

17. The method of claim 10 wherein the first dielectric layer and the second dielectric layer are continuous on sides and a bottom of the first opening and the second opening, respectively.

18. A semiconductor device comprising:

a semiconductor substrate comprising a first portion and a second portion;

a first nitrided oxide layer having a first nitride oxide thickness formed on the first portion of the semiconductor substrate, a gate on the first nitrided oxide layer and an interlevel dielectric layer on the first nitrided oxide layer and adjacent to the gate, the gate comprising a first dielectric layer and a first metallic gate material;

a second nitrided oxide layer having a second nitrided oxide thickness on the second portion of the semiconductor substrate and having a gap where the second nitrided oxide layer is not on the semiconductor substrate, a gate positioned in the gap so as to be in contact with the semiconductor substrate, and the interlevel dielectric layer on the second nitrided oxide layer and adjacent to the gate, the gate comprising a second dielectric layer and a second metallic gate material;

wherein the first nitrided oxide layer has a greater amount of nitride than the second nitrided oxide layer.

19. The semiconductor device of claim 18 wherein the first nitrided oxide layer and the first dielectric layer together have a first undergate thickness and the second dielectric layer has a second undergate thickness such that the first undergate thickness is greater than the second undergate thickness.

20. The semiconductor device of claim 18 wherein the first dielectric layer and the second dielectric layer are continuous on sides and a bottom of the first metallic gate material and the second metallic gate material, respectively.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052644/0868 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2016
From: CAO, QING; CHENG, KANGGUO; LI, ZHENGWEN; LIU, FEI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 039359/0606 →
Continuity (1)
Related Publication 20180040515A1 · Feb 8, 2018