IP Library Granted Patent US 9,536,832
Granted Patent B1
US 9,536,832 · App. 14/983,643 · Granted Jan 3, 2017

Junctionless back end of the line via contact

Inventor: Effendi Leobandung (Stormville, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L23/5283H01L21/32134H01L21/7684H01L21/76802H01L21/76832H01L21/76843H01L21/76883H01L23/5226H01L23/53238
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Quick Facts
Patent No.
US 9,536,832
App. No.
14/983,643
Granted
Jan 3, 2017
Kind
B1
Abstract

A method of forming an interconnect structure includes providing a first dielectric layer, patterning a wire opening in a first dielectric layer, lining the wire opening with a metal liner and includes filling the wire opening with a first conductive material. The method also includes depositing a first cap on the first dielectric layer, depositing a second dielectric layer, and patterning a via trench in the second dielectric layer. The method also includes depositing a metal liner, removing the metal liner from a via junction, and enlarging the contact area. The method also includes filling the via trench with a second conductive material to form a via.

Claims (32)

1. A method of forming an interconnect structure, the method comprising:

providing a first dielectric layer,

patterning a wire opening in a first dielectric layer,

lining the wire opening with a metal liner,

filling the wire opening with a first conductive material,

depositing a first cap on the first dielectric layer to form a first device layer, the first device layer comprising the first dielectric layer and the first cap,

depositing a second dielectric layer on the first device layer,

patterning a via trench in the second dielectric layer, wherein the via trench includes a via junction at the top of the second conductive material,

depositing a metal liner,

removing the metal liner from a via junction,

enlarging the contact area, and

filling the via trench with a second conductive material to form a via.

2. The method of claim 1 , wherein filling the via trench with a second conductive material comprises seeding the second conductive material from a surface of the first conductive material.

3. The method of claim 1 , the method further comprising planarizing the structure after filling the via trench with a second conductive material.

4. The method of claim 1 , wherein the first conductive material and the second conductive material are the same material.

5. The method of claim 4 , wherein the first conductive material and the second conductive material are copper.

6. The method of claim 1 , wherein the first dielectric layer and the second dielectric layer are the same material.

7. The method of claim 1 , wherein removing the metal liner from the via junction comprises reactive ion etching.

8. The method of claim 1 , further comprising undercutting the first conductive material with isotropic wet etching before filling the via trench with the second conductive material.

9. A method of forming an interconnect structure, the method comprising:

depositing an interlayer dielectric on a bottom interconnect layer, the bottom interconnect layer comprising a bottom dielectric layer and a first material,

patterning a trench in the interlayer dielectric, the trench extending through the interlayer dielectric to the top of the first material,

depositing a metal liner on the patterned interlayer dielectric,

anisotropically etching the liner to remove the liner from the bottom of the trench,

isotropically etching the structure to remove a portion of the first material, and

depositing a second material to fill the trench.

10. The method of claim 9 , wherein the interlayer dielectric is a dielectric material having a dielectric constant less than 4.

11. The method of claim 9 , wherein the first material and the second material are the same material.

12. The method of claim 11 , wherein the first material and the second material are copper.

13. The method of claim 9 , wherein the second material is a sacrificial material.

14. The method of claim 9 , further comprising depositing a first cap on the bottom interconnect layer.

15. The method of claim 9 , further comprising depositing a second cap on the interlayer dielectric.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052644/0868 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2015
From: LEOBANDUNG, EFFENDI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037380/0862 →