Integrated gate driver
View Patent ↗A method is presented for forming a semiconductor device. The method may include forming a first gate structure on a first portion of a semiconductor material located on a surface of an insulating substrate, the first gate structure including a first sacrificial layer and a second sacrificial layer and forming a second gate structure on a second portion of the semiconductor material located on the surface of the insulating substrate, the second gate structure including a third sacrificial layer. The method further includes etching the first and second dielectric sacrificial layers to create a first contact region within the first gate structure and etching the third dielectric sacrificial layer to create a second contact region within the second gate structure. The method further includes forming silicide in at least the first and second contact regions of the first and second gate structures, respectively.
1. A method of forming a semiconductor device, comprising:
forming a first gate structure on a first portion of a semiconductor material located on a surface of an insulating substrate, the first gate structure including a first sacrificial layer and a second sacrificial layer;
forming a second gate structure on a second portion of the semiconductor material located on the surface of the insulating substrate, the second gate structure including an intrinsic layer, a doped layer, and a third sacrificial layer, the intrinsic layer directly contacting the second portion of the semiconductor material;
etching the first sacrificial layer to create a first contact region within the first gate structure;
etching the third sacrificial layer to create a second contact region within the second gate structure; and
forming silicide in the first and second contact regions of the first and second gate structures, respectively.
2. The method of claim 1 , wherein the first gate structure is a depletion-mode MOSFET (metal oxide semiconductor field effect transistor) and the second gate structure is a HJFET (heterojunction field effect transistor).
3. The method of claim 1 , wherein the semiconductor material located on the surface of the insulating substrate is a LTPS (low-temperature poly-silicon) material.
4. The method of claim 1 , wherein the first and third sacrificial layers are dielectric layers, and the second sacrificial layer is a hydrogenated amorphous silicon layer.
5. The method of claim 1 , wherein the doped layer of the second gate structure has a dopant type opposite a dopant type of the second portion of the semiconductor material.
6. The method of claim 5 , wherein hydrogenated silicon is grown before etching of the first sacrificial layer of the first gate structure and the third sacrificial layer of the second gate structure.
7. The method of claim 6 , wherein, after etching, crystalline hydrogenated silicon remains adjacent the first and second gate structures.
8. The method of claim 7 , wherein the crystalline hydrogenated silicon has a second dopant type, the second dopant type being opposite the first dopant type of the second gate structure.
9. A method of forming a semiconductor device, comprising:
forming a first gate structure on a first portion of a semiconductor material located on a surface of an insulating substrate, the first gate structure including a first sacrificial layer and a first metal layer;
forming a second gate structure on a second portion of the semiconductor material located on the surface of the insulating substrate, the second gate structure including an intrinsic layer, a doped hydrogenated silicon layer, and a second sacrificial layer, the intrinsic layer directly contacting the second portion of the semiconductor material;
forming silicide adjacent the first and second gate structures;
etching the first sacrificial layer to expose the first metal layer above the first gate structure; and
etching the second sacrificial layer to expose the second metal layer above the second gate structure.
10. The method of claim 9 , wherein the first gate structure is a depletion-mode MOSFET and the second gate structure is a HJFET.
11. The method of claim 9 , wherein the semiconductor material located on the surface of the insulating substrate is a LTPS (low-temperature poly-silicon) material.
12. The method of claim 9 , wherein the doped layer of the second gate structure has a dopant type opposite a dopant type of the second portion of the semiconductor material.
13. The method of claim 12 , wherein hydrogenated silicon is grown before etching of the first and second sacrificial layers of the first and second gate structures, respectively.
14. The method of claim 13 , wherein, after etching, crystalline hydrogenated silicon remains adjacent the first and second gate structures.
15. The method of claim 14 , wherein the crystalline hydrogenated silicon has a second dopant type, the second dopant type being opposite the first dopant type of the second gate structure.
16. The method of claim 9 , wherein hydrogenated silicon is grown and a metal layer is placed over the hydrogenated silicon, the hydrogenated silicon and metal layer extending over the semiconductor material and onto a portion of the first and second gate structures.