IP Library Granted Patent US 10,396,165
Granted Patent B2
US 10,396,165 · App. 15/902,515 · Granted Aug 27, 2019

Thin low defect relaxed silicon germanium layers on bulk silicon substrates

Inventors: Praneet Adusumilli (Albany, NY); Keith E. Fogel (Hopewell Junction, NY); Alexander Reznicek (Troy, NY); Oscar van der Straten (Guilderland Center, NY)
Assignee: International Business Machines Corporation
H01L29/32H01L21/0245H01L21/0251H01L21/0262H01L21/02381H01L21/02532H01L21/02658H01L21/02664H01L29/161
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Quick Facts
Patent No.
US 10,396,165
App. No.
15/902,515
Granted
Aug 27, 2019
Kind
B2
Abstract

A strain relaxed silicon germanium layer that has a low defect density is formed on a surface of a silicon substrate without causing wafer bowing. The strain relaxed silicon germanium layer is formed using multiple epitaxial growing, bonding and transferring steps. In the present application, a thick silicon germanium layer having a low defect density is grown on a transferred portion of a topmost silicon germanium sub-layer of an initial strain relaxed silicon germanium graded buffer layer and then bonded to a silicon substrate. A portion of the thick silicon germanium layer is then transferred to the silicon substrate. Additional steps of growing a thick silicon germanium layer having a low defect density, bonding and layer transfer may be performed as necessary.

Claims (18)

1. A semiconductor structure comprising:

a strain relaxed silicon germanium layer having a thickness from 50 nm to 1000 nm and a defect density of less than 100 defect atoms/cm 2 located directly on a surface of a silicon substrate, wherein lattices of the strain relaxed silicon germanium layer and the silicon substrate are misaligned.

2. The semiconductor structure of claim 1 , wherein the strain relaxed silicon germanium layer has a germanium content from 20 atomic percent germanium to 25 atomic percent germanium.

3. The semiconductor structure of claim 1 , wherein a dislocation network is present at an interface of the strain relaxed silicon germanium layer and the silicon substrate.

4. The semiconductor structure of claim 1 , wherein the strain relaxed silicon germanium layer is devoid of threading dislocation defects.

5. The semiconductor structure of claim 1 , wherein the silicon substrate is a bulk substrate.

6. The semiconductor structure of claim 1 , wherein the silicon substrate is single crystalline.

7. The semiconductor structure of claim 1 , wherein the silicon substrate is devoid of wafer bowing.

8. The semiconductor structure of claim 1 , wherein a bonding interface is located between the silicon substrate and the strain relaxed silicon germanium layer.

9. A semiconductor structure comprising:

a strain relaxed silicon germanium layer having a thickness from 50 nm to 1000 nm and devoid of threading dislocation defects located directly on a surface of a silicon substrate, wherein lattices of the strain relaxed silicon germanium layer and the silicon substrate are misaligned and the silicon substrate is devoid of wafer bowing.

10. The semiconductor structure of claim 9 , wherein the strain relaxed silicon germanium layer has a germanium content from 20 atomic percent germanium to 25 atomic percent germanium.

11. The semiconductor structure of claim 9 , wherein a dislocation network is present at an interface of the strain relaxed silicon germanium layer and the silicon substrate.

12. The semiconductor structure of claim 9 , wherein the silicon substrate is a bulk substrate.

13. The semiconductor structure of claim 9 , wherein the silicon substrate is single crystalline.

14. A semiconductor structure comprising:

a strain relaxed silicon germanium layer having a germanium content from 20 atomic percent germanium to 25 atomic percent germanium, a thickness from 50 nm to 1000 nm and a defect density of less than 100 defect atoms/cm 2 located directly on a surface of a single crystalline silicon substrate, wherein lattices of the strain relaxed silicon germanium layer and the single crystalline silicon substrate are misaligned, wherein a dislocation network is present at an interface of the strain relaxed silicon germanium layer and the silicon substrate, and wherein the silicon substrate is devoid of wafer bowing.

15. The semiconductor structure of claim 14 , wherein the strain relaxed silicon germanium layer is devoid of threading dislocation defects.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052644/0868 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2018
From: ADUSUMILLI, PRANEET; FOGEL, KEITH E.; REZNICEK, ALEXANDER; VAN DER STRATEN, OSCAR
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 045006/0468 →
Continuity (2)
Division 15271939 · Sep 21, 2016
Related Publication 20180182720A1 · Jun 28, 2018