Semiconductor device with self-aligned carbon nanotube gate
A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.
1. A method for forming a semiconductor device, the method comprising:
forming a channel layer on a substrate;
depositing a gate dielectric on the channel layer;
removing an exposed portion of the gate dielectric to expose a first source/drain region and a second source/drain region of the channel layer;
forming a first source/drain contact on the first source/drain region and a second source/drain contact on the second source/drain region;
forming a cap layer over the first source/drain contact and the second source/drain contact;
forming spacers adjacent to sidewalls of the first source/drain contact and the second source/drain contact;
forming an oxide region in the cap layer; and
depositing a carbon material on an exposed portion of the gate dielectric.
2. The method of claim 1 , wherein the forming spacers adjacent to sidewalls of the source/drain contacts comprises:
depositing a layer of spacer material on exposed portions of the gate dielectric, the first source/drain contact, the second source/drain contact, and the cap layer; and
removing portions of the layer of spacer material to form the spacers.
3. The method of claim 2 , wherein the spacers are arranged on the gate dielectric.
4. The method of claim 1 , wherein the carbon material partially forms a gate stack on the gate dielectric.
5. The method of claim 1 , wherein the carbon material includes a carbon nanotube.
6. The method of claim 5 , wherein the carbon nanotube is formed by a chemically self-assembled carbon nanotube formation process.
7. The method of claim 1 , wherein the carbon material forms a gate stack on the gate dielectric.
8. The method of claim 1 , further comprising:
patterning a mask on the gate dielectric prior to removing the exposed portion of the gate dielectric; and
removing the mask after forming the cap layer.
9. The method of claim 1 , wherein the gate dielectric comprises HfO 2 .
10. The method of claim 1 , further comprising: implanting ions on the first source/drain region and the second source/drain region after removing the exposed part of the gate dielectric.
11. A method for forming a semiconductor device, the method comprising:
forming a channel layer on a substrate;
depositing a gate dielectric on the channel layer;
removing an exposed portion of the gate dielectric to expose a first source/drain region and a second source/drain region of the channel layer;
forming a first source/drain contact on the first source/drain region and a second source/drain contact on the second source/drain region;
forming a cap layer over the first source/drain contact and the second source/drain contact;
forming spacers adjacent to sidewalls of the first source/drain contact and the second source/drain contact;
forming an oxide region in a portion of the cap layer; and
depositing a carbon material on an exposed portion of the gate dielectric.
12. The method of claim 11 , wherein the forming spacers adjacent to sidewalls of the source/drain contacts comprises:
depositing a layer of spacer material on exposed portions of the gate dielectric, the first source/drain contact, the second source/drain contact, and the cap layer; and
removing portions of the layer of spacer material to form the spacers.
13. The method of claim 12 , wherein the spacers are arranged on the gate dielectric.
14. The method of claim 11 , wherein the carbon material partially forms a gate stack on the gate dielectric.
15. The method of claim 11 , wherein the carbon material includes a carbon nanotube.
16. The method of claim 15 , wherein the carbon nanotube is formed by a chemically self-assembled carbon nanotube formation process.
17. The method of claim 11 , wherein the carbon material forms a gate stack on the gate dielectric.
18. The method of claim 11 , further comprising:
patterning a mask on the gate dielectric prior to removing the exposed portion of the gate dielectric; and
removing the mask after forming the cap layer.
19. The method of claim 11 , wherein the gate dielectric comprises HfO 2 .
20. The method of claim 11 , further comprising: implanting ions on the first source/drain region and the second source/drain region after removing the exposed part of the gate dielectric.