Capacitor in strain relaxed buffer
Aspects include a semiconductor structure and fabrication method. A semiconductor structure may include alternating first and second crystalline layers and a capacitor. The capacitor may include a first terminal, a second terminal, and a dielectric. The first terminal may include a first central portion and first lobes extending laterally from the first central portion. The second terminal may include a second central portion and second lobes extending laterally from the second central portion. A portion of the second lobes may be fitted between consecutive first lobes. The fabrication method may include forming alternating first and second crystalline layers, forming a first trench, selectively etching the first crystalline layers within the first trench, depositing a dielectric in the first trench, filling the first trench with a metal, forming a second trench, etching the first and second crystalline layers within the second trench, and filling the second trench with a metal.
1. A semiconductor fabrication method comprising:
epitaxially growing a strain relaxed buffer on a substrate, the strain relaxed buffer comprising a plurality of first crystalline layers and a plurality of second crystalline layers arranged alternately;
epitaxially growing a strained crystalline layer on the strain relaxed buffer;
forming a protective layer over the strained crystalline layer;
forming a first trench through the protective layer, the strained crystalline layer, and the strain relaxed buffer;
selectively etching the plurality of first crystalline layers from with the first trench to create a plurality of first spaces extending laterally from the first trench;
depositing a dielectric along surfaces of the first trench and the plurality of first spaces using atomic layer deposition;
filling the first trench and the plurality of first spaces with a metal using atomic layer deposition;
forming a second trench through the protective layer, the strained crystalline layer, and the strain relaxed buffer;
etching the plurality of first crystalline layers and the plurality of second crystalline layers from within the second trench to expose the dielectric and form a cavity and a plurality of second spaces extending laterally from the first trench; and
filling the cavity and the plurality of second spaces with the metal using atomic layer deposition.
2. The method of claim 1 , wherein the plurality of first crystalline layers comprises a plurality of SiGe layers, wherein the Ge concentration of the plurality of SiGe layers is approximately 25%.
3. The method of claim 2 , wherein the selectively etching the plurality of first crystalline layers comprises etching using an HCl gas.
4. The method of claim 1 , wherein the plurality of second crystalline layers comprises a plurality of Si layers.
5. The method of claim 4 , wherein the etching the plurality of first crystalline layers and the plurality of second crystalline layers from within the second trench comprises etching with HCl and etching with ammonia.
6. The method of claim 1 , wherein the dielectric comprises a SiO 2 layer having a thickness in a range of 2-10 nm.
7. The method of claim 1 , wherein the strain relaxed buffer has a thickness in a range of 1-5 μm.
8. The method of claim 1 , wherein each of the plurality of first crystalline layers and each of the plurality of second crystalline layers has a thickness in a range of 10-50 nm.
9. A semiconductor structure comprising:
a strain relaxed buffer comprising a plurality of first crystalline layers and a plurality of second crystalline layers, wherein the first crystalline layers and second crystalline layers are arranged alternately; and
a capacitor provided inside the strain relaxed buffer; the capacitor comprising:
a first capacitor terminal;
a second capacitor terminal; and
a dielectric provided between the first capacitor terminal and the second capacitor terminal;
wherein the first capacitor terminal comprises:
a first capacitor terminal central portion extending through the first crystalline layers and the second crystalline layers; and
a plurality of first capacitor terminal lobes extending laterally from the first capacitor terminal central portion;
the second capacitor terminal comprises:
a second capacitor terminal central portion extending through the first crystalline layers and the second crystalline layers; and
a plurality of second capacitor terminal lobes extending laterally from the second capacitor terminal central portion;
the first capacitor terminal and the second capacitor terminal are arranged such that a portion of the plurality of second capacitor terminal lobes are fitted between consecutive first capacitor terminal lobes; and
the first capacitor terminal and the second capacitor terminal comprise a metal.
10. The semiconductor structure of claim 9 , wherein the plurality of first crystalline layers comprises a plurality of SiGe layers, wherein the Ge concentration of the plurality of SiGe layers is approximately 25%.
11. The semiconductor structure of claim 9 , wherein the plurality of second crystalline layers comprises a plurality of Si layers.
12. The semiconductor structure of claim 9 , wherein the dielectric comprises a SiO 2 layer having a thickness in a range of 2-10 nm.
13. The semiconductor structure of claim 9 , further comprising:
a third capacitor terminal formed on a side of the first capacitor terminal opposite to second capacitor terminal;
wherein the third capacitor comprises:
a third capacitor terminal central portion extending through the first crystalline layers and the second crystalline layers; and
a plurality of third capacitor terminal lobes extending laterally from the third capacitor terminal central portion;
wherein the first capacitor terminal and the third capacitor terminal are arranged such that a portion of the plurality of third capacitor terminal lobes are fitted between consecutive first capacitor terminal lobes.
14. The semiconductor structure of claim 13 , wherein the second semiconductor terminal and the third semiconductor terminal are electrically connected.
15. The semiconductor structure of claim 9 , wherein the stress relaxed buffer has a thickness in a range of 1-5 μm.
16. The semiconductor structure of claim 9 , wherein each of the plurality of first crystalline layers and each of the plurality of second crystalline layers has a thickness in a range of 10-50 nm.
17. A semiconductor structure comprising:
a strain relaxed buffer comprising a plurality of first crystalline layers and a plurality of second crystalline layers, wherein the first crystalline layers and second crystalline layers are arranged alternately; and
a capacitor provided inside the strain relaxed buffer; the capacitor comprising:
a plurality of first capacitor terminals;
a plurality of second capacitor terminals; and
a dielectric provided between the plurality of first capacitor terminals and the plurality of second capacitor terminals;
wherein each of the plurality of first capacitor terminals comprises:
a first capacitor terminal central portion extending through the first crystalline layers and the second crystalline layers; and
a plurality of first capacitor terminal lobes extending laterally from the first capacitor terminal central portion;
each of the plurality of second capacitor terminal comprises:
a second capacitor terminal central portion extending through the first crystalline layers and the second crystalline layers; and
a plurality of second capacitor terminal lobes extending laterally from the second capacitor terminal central portion;
each of the plurality of first capacitor terminals are mutually electrically connected;
each of the plurality of second capacitor terminals are mutually electrically connected;
wherein each first capacitor terminal central portion of the plurality of first capacitor terminals are mutually parallel and extend in a longitudinal direction;
wherein each second terminal capacitor central portion of the plurality of second capacitor terminals are mutually parallel; and
a portion of the plurality of second capacitor terminals are provided between consecutive first capacitor terminals and arranged such that a portion of the plurality of second capacitor terminal lobes are fitted between consecutive first capacitor terminal lobes.