Vertical transistor top epitaxy source/drain and contact structure
An nFET vertical transistor is provided in which a p-doped top source/drain structure is formed in contact with an n-doped semiconductor region that is present on a topmost surface of a vertical nFET channel. The p-doped top source/drain structure is formed utilizing a low temperature (550° C. or less) epitaxial growth process.
1. A semiconductor structure comprising:
an nFET vertical transistor located in an nFET device region of a semiconductor substrate, the nFET vertical transistor comprises:
an nFET bottom source/drain structure comprising an n-doped semiconductor material region and an n-doped extension region;
a vertical nFET channel extending upwards from the n-doped extension region;
an nFET gate stack located on each sidewall of the vertical nFET channel;
an n-doped semiconductor region located on a topmost surface of the vertical nFET channel;
a p-doped top source/drain structure located on physically exposed surfaces of the n-doped semiconductor region;
an nFET bottom gate spacer separating a topmost surface of the nFET bottom source/drain structure from a bottommost surface of the nFET gate stack; and
an nFET top gate spacer located on a topmost surface of each nFET gate stack and contacting a lower portion of a sidewall of the n-doped semiconductor region, wherein the nFET top gate spacer has a topmost surface that is located beneath a topmost surface of the n-doped semiconductor region.
2. The semiconductor structure of claim 1 , wherein sidewalls of the n-doped extension region, the vertical nFET channel, and the n-doped semiconductor region are vertically aligned to each other.
3. The semiconductor structure of claim 1 , wherein a sidewall of the nFET bottom gate spacer contacts a bottom portion of a sidewall of the n-doped extension region.
4. The semiconductor structure of claim 1 , wherein the p-doped top source/drain structure has a faceted top surface.
5. The semiconductor structure of claim 1 , further comprising a planarizing dielectric material structure laterally surrounding and present above the nFET vertical transistor.
6. The semiconductor structure of claim 1 , further comprising a p-doped semiconductor material punch through stop (PTS) layer located between a bottommost surface of the n-doped semiconductor material region and a topmost surface of the semiconductor substrate.
7. The semiconductor structure of claim 1 , wherein the n-doped semiconductor region has an n-type dopant concentration greater than 1×10 21 atoms/cm 3 , and the p-doped top source/drain structure comprises a semiconductor material having a p-type dopant concentration greater than 1×10 21 atoms/cm 3 .
8. The semiconductor structure of claim 7 , wherein the p-doped top source/drain structure comprises a boron doped silicon germanium alloy.
9. The semiconductor structure of claim 1 , further comprising a pFET vertical transistor located in a pFET device region of the semiconductor substrate, the pFET vertical transistor comprising:
a pFET bottom source/drain structure comprising a p-doped semiconductor material region and a p-doped extension region;
a vertical pFET channel extending upwards from the p-doped extension region;
a pFET gate stack located on each sidewall of the vertical pFET channel; and
a pFET top source/drain structure located on a topmost surface of the vertical pFET channel.
10. The semiconductor structure of claim 9 , wherein the pFET top source/drain structure of the pFET vertical transistor and the p-doped top source/drain structure of the nFET vertical transistor both comprise a boron doped silicon germanium alloy.
11. A semiconductor structure comprising:
an nFET vertical transistor located in an nFET device region of a semiconductor substrate, the nFET vertical transistor comprises:
an nFET bottom source/drain structure comprising an n-doped semiconductor material region and an n-doped extension region;
a vertical nFET channel entirely composed of an undoped semiconductor material extending upwards from the n-doped extension region;
an nFET gate stack located on each sidewall of the vertical nFET channel;
an n-doped semiconductor region located on a topmost surface of the vertical nFET channel;
a p-doped top source/drain structure located on physically exposed surfaces of the n-doped semiconductor region;
an nFET bottom gate spacer separating a topmost surface of the nFET bottom source/drain structure from a bottommost surface of the nFET gate stack; and
an nFET top gate spacer located on a topmost surface of each nFET gate stack and contacting a lower portion of a sidewall of the n-doped semiconductor region, wherein the nFET top gate spacer has a topmost surface that is located beneath a topmost surface of the n-doped semiconductor region.