Vertical CMOS devices with common gate stacks

1. A semiconductor structure, comprising:

a first nanowire of a first material disposed on a top surface of a substrate;

at least a second nanowire of a second material different than the first material disposed on the top surface of the substrate; and

a common gate stack surrounding the first nanowire and the second nanowire;

wherein the first nanowire and the second nanowire are vertical with respect to a horizontal plane of the top surface of the substrate;

wherein the first nanowire forms at least a portion of a negative field-effect transistor (NFET) vertical transport channel of a complementary metal-oxide-semiconductor (CMOS) device;

wherein the second nanowire forms at least a portion of a positive field-effect transistor (PFET) vertical transport channel of the CMOS device; and

wherein the first material comprises a group III-V material and the second material comprises a group IV material.

2. The semiconductor structure of claim 1 , wherein the first material comprises indium gallium arsenide (InGaAs) and the second material comprises germanium (Ge).

3. The semiconductor structure of claim 1 , wherein the first nanowire comprises a first dummy channel surrounded by the first material and the second nanowire comprises a second dummy channel surrounded by the second material, the first dummy channel and the second dummy channel comprising a third material different than the first material and the second material.

4. The semiconductor structure of claim 3 , wherein the first material comprises indium gallium arsenide (InGaAs), the second material comprises germanium (Ge) and the third material comprises gallium arsenide (GaAs).

5. The semiconductor structure of claim 1 , wherein the first nanowire comprises a channel of the first material and the second nanowire comprises a dummy channel of the first material surrounded by the second material.

6. The semiconductor structure of claim 5 , wherein the first material comprise indium gallium arsenide (InGaAS) and the second material comprises germanium (Ge).

7. An integrated circuit comprising:

at least one complementary metal-oxide-semiconductor (CMOS) device, the CMOS device comprising:

a first nanowire of a first material disposed on a top surface of a substrate;

at least a second nanowire of a second material different than the first material disposed on the top surface of the substrate; and

a common gate stack surrounding the first nanowire and the second nanowire;

wherein the first nanowire and the second nanowire are vertical with respect to a horizontal plane of the top surface of the substrate;

wherein the first nanowire forms at least a portion of a negative field-effect transistor (NFET) vertical transport channel of the CMOS device;

wherein the second nanowire forms at least a portion of a positive field-effect transistor (PFET) vertical transport channel of the CMOS device; and

wherein the first material comprises a group III-V material and the second material comprises a group IV material.

8. The integrated circuit of claim 7 , wherein the first material comprises indium gallium arsenide (InGaAs) and the second material comprises germanium (Ge).

9. A method for forming a semiconductor structure, comprising:

forming a first nanowire of a first material on a top surface of a substrate;

forming a second nanowire of a second material different than the first material on the top surface of the substrate; and

forming a common gate stack surrounding the first nanowire and the second nanowire;

wherein the first nanowire and the second nanowire are vertical with respect to a horizontal plane of the top surface of the substrate;

wherein the first nanowire forms at least a portion of a negative field-effect transistor (NFET) vertical transport channel of the CMOS device;

wherein the second nanowire forms at least a portion of a positive field-effect transistor (PFET) vertical transport channel of the CMOS device; and

wherein the first material comprises a group III-V material and the second material comprises a group IV material.

10. The method of claim 9 , wherein:

forming the first nanowire comprises forming a first dummy channel surrounded by the first material;

forming the second nanowire comprises forming a second dummy channel surrounded by the second material; and

the first dummy channel and the second dummy channel comprise a third material different than the first material and the second material.

11. The method of claim 10 , wherein the first material comprises indium gallium arsenide (InGaAs), the second material comprises germanium (Ge) and the third material comprises gallium arsenide (GaAs).

12. The method of claim 9 , wherein:

forming the first nanowire comprises forming a channel of the first material;

forming the second nanowire comprises forming a dummy channel of the first material surrounded by the second material.

13. The method of claim 12 , wherein the first material comprises indium gallium arsenide (InGaAS) and the second material comprises germanium (Ge).

14. The method of claim 9 , further comprising:

forming a first bottom source/drain region in a first portion of the top surface of the substrate;

forming a second bottom source/drain region in a second portion of the top surface of the substrate; and

forming a shallow trench isolation region between the first bottom source/drain and the second bottom source/drain.

15. The method of claim 14 , further comprising:

forming a first insulator over at least a portion of the first bottom source/drain region, the shallow trench isolation region and the second bottom source/drain region; and

patterning the first insulator to form at least a first exposed region over the first bottom source/drain region and at least a second exposed region over the second bottom source/drain region.

16. The method of claim 15 , further comprising:

forming at least a first dummy channel over the first exposed region and at least a second dummy channel over the second exposed region;

forming a first layer on a top surface and sidewalls of the first dummy channel protruding above the first insulator and a second layer on a top surface and sidewalls of the second dummy channel protruding above the first insulator, the first layer comprising the first material and the second layer comprising the second material; and

forming the common gate stack over the first insulator, the first layer and the first second layer.

17. The method of claim 16 , further comprising:

forming gate material over the common gate stack and recessing the gate material to remove a portion of the common gate stack to expose a first portion of the first layer and a second portion of the second layer;

forming a second insulator over the gate material;

doping the exposed first portion of the first layer with a first dopant type;

doping the exposed second portion of the second layer with a second dopant type different than the first dopant type.

18. The method of claim 17 , further comprising:

forming a metal layer over the second insulator, the exposed first portion of the first layer and the exposed second portion of the second layer; and

annealing the structure to form a first top source/drain from the metal layer and the exposed first portion of the first layer on the first dummy channel and a second top source/drain from the metal layer and the exposed second portion of the second layer on the second dummy channel.

19. The method of claim 18 , further comprising:

forming an oxide on the top surface of the first bottom source/drain region and the second bottom source/drain region, the oxide surrounding the common gate stack, the gate material, the first top source/drain region and the second top source/drain region;

patterning the oxide to expose portions of the first bottom source/drain region, the second bottom source/drain region, the first top source/drain region, the second top source/drain region and the gate material; and

forming contacts to the first bottom source/drain region, the second bottom source/drain region, the first top source/drain region, the second top source/drain region and the gate material in the portions exposed by the patterned oxide.