Forming chamferless vias using thermally decomposable porefiller
A method for forming chamferless vias comprises receiving a substrate stack comprising a hard mask layer, a porous dielectric layer underlying the hard mask layer, a cap layer underlying the dielectric layer, and a conductive layer underlying the cap layer. The hard mask layer is opened to reveal a portion of the dielectric layer. A plurality of vias are opened to extend through the dielectric layer and the cap layer. A pore filling material comprising a thermally decomposable polymer is deposited into the vias. The pore filling material in the vias is hardened and driven into the pores of the dielectric layer adjacent to the vias by an annealing process. The hard mask layer is removed. A trench is patterned and etched coincident with the vias. A dissipation process is conducted to remove the pore filling material.
1. A method for forming chamferless vias, the method comprising:
receiving a substrate stack comprising a hard mask layer, a porous dielectric layer underlying the hard mask layer, a cap layer underlying the dielectric layer, and a conductive layer underlying the cap layer;
opening a portion of the hard mask layer to reveal a portion of the dielectric layer;
opening a plurality of vias to extend through the dielectric layer and the cap layer;
depositing into the vias a pore filling material comprising a thermally decomposable polymer wherein the pore filling material alone and the dielectric layer containing the pore filling material have different etch selectivities;
annealing to harden the pore filling material in the vias and drive the pore filling material into pores of the dielectric layer adjacent to the vias;
patterning and etching a trench coincident with the vias wherein etching the trench further comprises selectively etching the pore filling material in the vias to control a plug height of the pore filling material;
removing the hard mask layer; and
conducting a dissipation process to remove the pore filling material.
2. The method of claim 1 , wherein the dielectric layer comprises an ultra-low-k dielectric.
3. The method of claim 1 , wherein the thermally decomposable polymer is selected to fill the pores of the dielectric layer in response to annealing.
4. The method of claim 1 , wherein annealing comprises heating the pore filling material to a temperature above a glass transition point of the pore filling material.
5. The method of claim 4 , wherein the temperature is approximately 200° C.
6. The method of claim 1 , wherein etching the trench comprises etching away a portion of the dielectric layer containing the pore filling material and a portion of the pore filling material.
7. The method of claim 1 , wherein the hard mask layer comprises one or more of SiO 2 , SiCOH, TiN, and SiN.
8. The method of claim 1 , wherein the dissipation process occurs at a temperature not higher than approximately 400° C.
9. The method of claim 1 , wherein the dissipation process occurs at or above approximately 350° C.
10. The method of claim 1 , wherein the dissipation process comprises one or more of a thermal anneal process, a UV anneal process, and a plasma assisted anneal process.
11. The method of claim 1 , further comprising:
filling the trench with a conductive material.