Patterned gate dielectrics for III-V-based CMOS circuits
Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.
1. A method for forming a plurality of semiconductor devices, comprising:
forming a first channel region on a first semiconductor region;
forming a second channel region on a second semiconductor region, the second semiconductor region being formed by removing a first semiconductor material from the second semiconductor region to form a trench, and filling the trench with a second semiconductor material that is different from the first semiconductor material of the first semiconductor region;
forming a gate dielectric layer over one or more of the first and second channel regions;
forming a nitrogen-containing layer on the gate dielectric layer; and
forming a gate on the gate dielectric.
2. The method of claim 1 , wherein the first semiconductor material is one of a group IV semiconductor and a III-V semiconductor and wherein the second semiconductor material is the other of the group IV semiconductor and the III-V semiconductor and wherein the first semiconductor region is coplanar with the second semiconductor region.
3. The method of claim 1 , further comprising forming a channel nitrogen-containing layer on one or more of the first and second channel regions before forming the gate dielectric layer.
4. The method of claim 3 , wherein forming the channel nitrogen-containing layer comprises forming the channel nitrogen-containing layer on only one of the first and second channel regions.
5. The method of claim 3 , wherein forming the channel nitrogen-containing layer comprises forming the channel nitrogen-containing layer on both the first and second channel regions.
6. The method of claim 1 , wherein forming the nitrogen-containing layer comprises treating a surface of the gate dielectric layer to form a nitrogen-containing gate dielectric layer.
7. The method of claim 6 , wherein forming the nitrogen-containing layer comprises one of performing an ammonia anneal and exposing the dielectric layer to a nitrogen plasma.
8. The method of claim 1 , wherein forming the gate dielectric layer and the gate comprise forming a first gate dielectric layer and a first gate over only one of the first and second channel regions, further comprising:
forming a second gate dielectric layer on the other of the first and second channel regions, wherein the second gate dielectric layer is formed from a dielectric material different from the material of the first gate dielectric layer; and
forming a second gate on the second dielectric layer, wherein the second gate is formed from a gate material different from the material of the first gate.
9. A semiconductor device, comprising:
a first channel region formed from a first semiconductor material;
a second channel region formed by removing a first semiconductor material from the second semiconductor region to form a trench, and filling the trench with a second semiconductor material, different from the first semiconductor material;
a nitrogen-containing layer on one or more of the first and second channel regions; and
a gate formed over the nitrogen-containing layer.
10. The semiconductor device of claim 9 , wherein the first semiconductor material is one of a group IV semiconductor and a III-V semiconductor and wherein the second semiconductor material is the other of the group IV semiconductor and the III-V semiconductor.
11. The semiconductor device of claim 9 , further comprising a gate dielectric layer, wherein the nitrogen-containing layer is formed on the top surface of the gate dielectric layer.
12. The semiconductor device of claim 9 , wherein the nitrogen-containing layer is formed on only the first channel region and the gate comprises a first gate over the first channel region, further comprising:
a first gate dielectric layer formed over the first channel region, under the first gate;
a second gate dielectric layer formed over the second channel region from a dielectric material different from the dielectric material of the first gate dielectric layer; and
a second gate formed on the second gate dielectric layer from a gate material different from the gate material of the first gate.