Method and structure of forming low resistance interconnects

1. A semiconductor structure comprising:

a combined via level/line level interconnect structure embedded in a first interconnect dielectric material layer, wherein said combined via level/line level interconnect structure comprises a dual damascene opening containing, from bottom to top, a via opening and a line opening, wherein the via opening and the line opening are in direct contact with each other; and

a line level interconnect structure embedded at least in part in a second interconnect dielectric material layer and located directly on at least a portion of said combined via level/line level interconnect structure, wherein said combined via level/line level interconnect structure further comprises a first conductive metal or metal alloy having a bamboo microstructure present in said via opening and line opening of said combined via level/line level interconnect structure, and said line level interconnect structure comprises a second conductive metal or metal alloy having a bamboo microstructure that is present in a line opening of said line level interconnect structure, wherein said line level interconnect structure is misaligned with said combined via level/line level interconnect structure, and wherein a metallic cap layer portion is located on a misaligned portion of said combined via level/line level interconnect structure and completely embedded in said second interconnect dielectric material, said metallic cap portion having a first side wall edge contacting a portion of said second interconnect dielectric material and a second side wall edge vertically aligned to a sidewall of said line opening in said second dielectric material layer and contacting said line level interconnect structure.

2. The semiconductor structure of claim 1 , wherein said first and second interconnect dielectric material layers are in direct physical contact with each other.

3. The semiconductor structure of claim 1 , wherein said combined via level/line level interconnect structure further includes a first diffusion barrier liner.

4. The semiconductor structure of claim 3 , wherein said line level interconnect structure further includes a second diffusion barrier liner.

5. The semiconductor structure of claim 1 , wherein said line level of said combined via level/line level interconnect structure has an aspect ratio of less than 2.5.

6. The semiconductor structure of claim 5 , wherein said line level interconnect structure has an aspect ratio of less than 2.5.

7. A method of forming a semiconductor structure, said method comprising:

forming a combined via level/line level interconnect structure embedded in a first interconnect dielectric material layer, wherein said combined via level/line level interconnect structure comprises a dual damascene opening containing, from bottom to top, a via opening and a line opening, wherein the via opening and the line opening are in direct contact with each other; and

forming a line level interconnect structure embedded at least in part in a second interconnect dielectric material layer and located directly on at least a portion of said combined via level/line level interconnect structure, wherein said combined via level/line level interconnect structure further comprises a first conductive metal or metal alloy having a bamboo microstructure present in said via opening and line opening of said combined via level/line level interconnect structure, and said line level interconnect structure comprises a second conductive metal or metal alloy having a bamboo microstructure that is present in a line opening of said line level interconnect structure, wherein said line opening of said line level interconnect structure is misaligned to said line opening of said combined via level/line level interconnect structure, and wherein a metallic capping layer is formed on exposed surface of said combined via level/line level interconnect structure prior to said forming said second interconnect dielectric material, and wherein said forming said line opening of said line level interconnect structure removes at least a portion of said metallic capping layer to provide a metallic cap layer portion located on a misaligned portion of said combined via level/line level interconnect structure and completely embedded in said second interconnect dielectric material, said metallic cap portion having a first side wall edge contacting a portion of said second interconnect dielectric material and a second side wall edge vertically aligned to a sidewall of said line opening in said second dielectric material layer and contacting said line level interconnect structure.

8. The method of claim 7 , wherein said forming said combined via level/line level interconnect structure embedded in said first interconnect dielectric material layer comprises:

providing said first interconnect dielectric material layer on a surface of a substrate;

forming said dual damascene opening in said first interconnect dielectric material layer;

forming a first conductive metal or metal alloy having a polycrystalline microstructure in said dual damascene opening;

annealing said first conductive metal or metal alloy to convert said polycrystalline microstructure of said first conductive metal or metal alloy into said bamboo microstructure; and

planarizing said first conductive metal or metal alloy having said bamboo microstructure to provide said combined via level/line level interconnect structure.

9. The method of claim 8 , further comprising:

forming a continuous layer of a first diffusion barrier material in said dual damascene opening prior to said forming said first conductive metal or metal alloy having said polycrystalline microstructure, and wherein said planarizing removes a portion of said continuous layer of said first diffusion barrier material from a topmost surface of said first interconnect dielectric material layer.

10. The method of claim 7 , wherein said forming said line level interconnect structure embedded in said second interconnect dielectric material layer comprises:

providing said second interconnect dielectric material layer atop said first interconnect dielectric material layer containing said combined via level/line level interconnect structure;

forming said line opening of said line level interconnect structure in said second interconnect dielectric material layer to expose a surface of said combined via level/line level interconnect structure;

forming a second metal or metal alloy having a polycrystalline microstructure in said line opening;

annealing said second conductive metal or metal alloy to convert said polycrystalline microstructure of said second conductive metal or metal alloy into said bamboo microstructure; and

planarizing said second conductive metal or metal alloy having said bamboo microstructure to provide said line level interconnect structure.

11. The method of claim 10 , further comprising:

forming a continuous layer of a second diffusion barrier material in said line opening of said line level interconnect structure prior to said forming said second metal or metal alloy having said polycrystalline microstructure, and wherein said planarizing removes a portion of said continuous layer of said second diffusion barrier material from a topmost surface of said second interconnect dielectric material layer.

12. The method of claim 7 , wherein said line level of said combined via level/line level interconnect structure has an aspect ratio of less than 2.5, and said line level interconnect structure has an aspect ratio of less than 2.5.