Hard masks for block patterning
Embodiments are directed to a method of forming a semiconductor device and resulting structures having a hard masks for sidewall image transfer (SIT) block patterning. The method includes forming a first hard mask on a substrate. Spacers are formed on the first hard mask, and a second hard mask is formed over the spacers. The second hard mask and a portion of the first hard mask are concurrently removed by the same hard mask removal process to expose a surface of the substrate. After concurrently removing the second hard mask and portions of the first hard mask, the heights of the spacers are substantially equal.
1. A semiconductor device comprising:
a dielectric layer formed on a substrate;
a planarization layer formed on the dielectric layer;
a hard mask formed on the dielectric layer, the hard mask patterned to expose a surface of the dielectric layer in a first region;
a first plurality of spacers on the hard mask in the first region and a second plurality of spacers on the hard mask in a second region; and
a gap filling layer over and between the second plurality of spacers;
wherein a height of each spacer of the first plurality of spacers is substantially equal to a height of each spacer of the second plurality of spacers.
2. The semiconductor device of claim 1 , wherein a height of the first plurality of spacers is less than about 20 nm.
3. The semiconductor device of claim 1 , wherein a centerline to centerline pitch between each of the first plurality of spacers is less than about 40 nm.
4. The semiconductor device of claim 1 , wherein reactive ion etching (RIE) is used to pattern of the hard mask.
5. The semiconductor device of claim 4 , wherein the RIE is selective to the first plurality of spacers.
6. The semiconductor device of claim 4 , wherein the RIE is selective to the planarization layer.
7. The semiconductor device of claim 4 , wherein the RIE is selective to the first plurality of spacers and the second plurality of spacers.
8. The semiconductor device of claim 1 , wherein the gap filling layer is etched selective to the first plurality of spacers.
9. The semiconductor device of claim 1 , wherein the first plurality of spacers are not exposed to a hard mask burn off.
10. The semiconductor device of claim 1 , wherein the hard mask is comprised of: a nitride, a silicon nitride, a metal nitride or a metal oxide.
11. The semiconductor device of claim 10 , wherein the hard mask is comprised of a titanium nitride (TiN) layer.
12. The semiconductor device of claim 11 , wherein the TiN layer has a thickness of about 25 nm.
13. The semiconductor device of claim 1 , wherein the first plurality of spacers reside in an open area and the second plurality of spacers reside in a block area.
14. The semiconductor device of claim 1 , wherein at least a portion of the mask is removed concurrently with a removal of another mask.