Superlattice lateral bipolar junction transistor
A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.
1. A bipolar junction transistor, comprising:
an intrinsic base including a superlattice stack including a plurality of alternating layers of semiconductor material;
a collector and emitter; and
an extrinsic base structure formed on the intrinsic base.
2. The transistor as recited in claim 1 , wherein the superlattice stack includes alternating materials in the alternating layers.
3. The transistor as recited in claim 1 , wherein the alternating layers include Si and Ge.
4. The transistor as recited in claim 1 , wherein the superlattice stack includes a bottom-most layer that extends below the collector and emitter to function as a seed layer to form the collector and emitter.
5. The transistor as recited in claim 1 , wherein the superlattice stack is formed on an extremely thin semiconductor-on-insulator (ETSOI) substrate.
6. The transistor as recited in claim 5 , wherein a semiconductor layer of the ETSOI substrate forms a layer of the superlattice stack.
7. The transistor as recited in claim 1 , further comprising a strained layer on which the superlattice stack is formed.
8. The transistor as recited in claim 7 , wherein the strained layer includes a mass variance configured to increase thermal conductivity of the strained layer by isotope enrichment of the strained layer.
9. The transistor as recited in claim 1 , wherein the superlattice stack includes a mass variance configured to increase thermal conductivity of the superlattice stack by isotope enrichment of the superlattice stack.
10. The transistor as recited in claim 1 , wherein the alternating layers are lattice mismatched to each other.
11. A bipolar junction transistor, comprising:
an extremely thin semiconductor-on-insulator substrate (ETSOI) having a semiconductor layer;
a superlattice stack including a plurality of alternating layers of semiconductor material wherein a first layer of the plurality of alternating layers includes the semiconductor layer;
an intrinsic base formed from the superlattice stack; and
an extrinsic base structure formed on the intrinsic base.
12. The transistor as recited in claim 11 , wherein the alternating layers include Si and Ge.
13. The transistor as recited in claim 11 , wherein the semiconductor layer extends below a collector and emitter to function as a seed layer to form the collector and emitter.
14. The transistor as recited in claim 11 , further comprising a strained layer on which the superlattice stack is formed.
15. The transistor as recited in claim 14 , wherein the strained layer includes a mass variance configured to increase thermal conductivity of the strained layer by isotope enrichment of the strained layer.
16. The transistor as recited in claim 11 , wherein the superlattice stack includes a mass variance configured to increase thermal conductivity of the superlattice stack by isotope enrichment of the superlattice stack.
17. The transistor as recited in claim 11 , wherein the alternating layers are lattice mismatched to each other.
18. The transistor as recited in claim 11 , wherein the superlattice stack includes alternating materials in the alternating layers.