Nanowire semiconductor device
A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a <110> orientation wherein the hard mask is oriented in the <112> direction, etching the silicon substrate to form a mandrel having (111) faceted sidewalls; forming a layer of insulator material on the substrate; forming a sacrificial stack comprising alternating layers of sacrificial material and dielectric material disposed on the layer of insulator material and adjacent to the mandrel; patterning and etching the sacrificial stack to form a modified sacrificial stack adjacent to the mandrel and extending from the mandrel; removing the sacrificial material from the modified sacrificial stack to form growth channels; epitaxially forming semiconductor in the growth channels; and etching the semiconductor to align with the end of the growth channels and form a semiconductor stack comprising alternating layers of dielectric material and semiconductor material.
1. A semiconductor device comprising a first vertical stack above an insulating layer and a second vertical stack above the insulating layer, wherein the first and second vertical stacks comprise a plurality of <111> III-V compound semiconductor nanowires.
2. The semiconductor device of claim 1 , further comprising dielectric material disposed between the nanowires.
3. The semiconductor device of claim 1 , wherein a bottom nanowire of the first vertical stack and a bottom nanowire of the second vertical stack are disposed over the insulating layer.
4. The semiconductor device of claim 1 , wherein the insulating layer is discontinuous.
5. The semiconductor device of claim 1 , wherein the nanowires have a thickness of 3 nanometers to 20 nanometers.
6. The semiconductor device of claim 1 , wherein the nanowires have a thickness of 5 nanometers to 10 nanometers.
7. A semiconductor device comprising a <110> silicon substrate and a vertical nanosheet stack formed above the substrate, the vertical nanosheet stack comprising a <111> III-V compound semiconductor nanosheet.
8. The semiconductor device of claim 7 , further comprising an insulating layer formed between the substrate and the nanosheet.
9. The semiconductor device of claim 8 , wherein the insulating layer is discontinuous.
10. The semiconductor device of claim 7 , wherein the nanosheet has a thickness of 3 nanometers to 20 nanometers.
11. The semiconductor device of claim 7 , wherein the nanosheet has a thickness of 5 nanometers to 10 nanometers.