Simplified gate stack process to improve dual channel CMOS performance
A semiconductor device and method of making the same wherein the semiconductor device includes a pFET region including a SiGe channel having a Si-rich top surface within the gate portion, and an nFET region including a Si channel. The method includes subjecting both the pFET and nFET regions to a single high-temperature anneal process thereby avoiding the need for an additional spike anneal process at RMG module.
1. A method of fabricating a semiconductor device, the method comprising:
forming at least one of a first semiconductor region and a second semiconductor region different from the first semiconductor region, wherein forming at least one of the first semiconductor region and second semiconductor region comprises:
forming a first semiconductor channel comprising a first semiconductor material;
forming a first set of spacers extending from the top surface of the semiconductor channel so as to define a first gate between the first set of spacers;
depositing a fist sacrificial material between the first set of spacers, the sacrificial material comprising a combination of the first semiconductor material and an oxide material
annealing the first sacrificial material to form a first semiconductor-rich surface on a portion of the top surface of the semiconductor channel between the first set of spacers,
wherein the first gate includes a first high-k dielectric layer in contact with the spacers, and a first metal gate material in contact with the high-k dielectric layer.
2. The method of claim 1 , wherein forming the first semiconductor region includes forming a p-field effect transistor (pFET) region, and wherein forming the pFET region further comprises:
forming a SiGe channel that defines the first semiconductor channel;
depositing the first sacrificial material comprising SiGeOx; and
annealing the first sacrificial material so that the SiGeOx chemically reacts with the SiGe channel to form a Si-rich region on a portion of the top surface of the SiGe channel that defines the semiconductor-rich surface, and
wherein forming the second semiconductor region includes forming an n-field effect transistor (nFET) region, wherein forming the n-field effect transistor (nFET) region further comprises:
forming a Si channel;
forming a second set of spacers extending from the top surface of the Si channel so as to define a second gate between the second set of spacers;
wherein the second gate includes a second high-k dielectric layer in contact with the second set of spacers, and a second metal gate material in contact with the second high-k dielectric layer.
3. The method of claim 2 further comprising forming a first high-k dielectric layer in contact with the first set of spacers.
4. The method of claim 3 further comprising forming a second high-k dielectric layer in contact with the second set of spacers.
5. The method of claim 4 , wherein the first high-k dielectric layer and second high-k dielectric layer are independently selected from silicon nitride, aluminum oxide, zirconium oxide, titanium oxide, tantalum pentoxide, barium-strontium-titanate, strontium-titanate-oxide, lead-zirconium-titanate, and combinations thereof.
6. The method of claim 3 further comprising forming a first ozone layer on the Si-rich layer.
7. The semiconductor device of claim 6 , further comprising forming the first ozone layer between the Si-rich layer and the first high-k dielectric layer.
8. The method of claim 7 further comprising forming a second ozone layer on the Si channel between the second set of spacers.
9. The method of claim 8 , further comprising forming the second ozone layer between the Si channel between the second high-k dielectric layer.
10. The method of claim 2 , further comprising forming source and drain regions within the n-field effect transistor (nFET) region and the p-field effect transistor (pFET) region.
11. The method of claim 2 , wherein the first gate material and second gate material are independently selected from TiN, TiAl, TaN, and combinations thereof.
12. The s method of claim 2 , wherein the Si-rich layer has a concentration of Ge that is at least 10% lower than the concentration of Ge in the SiGe channel.
13. The method of claim 2 , wherein the Si-rich layer has a concentration of Ge that is at least 5% lower than the concentration of Ge in the SiGe channel.
14. A method of fabricating a semiconductor device comprising:
forming at least one of a first semiconductor region and a second semiconductor region different from the first semiconductor region, the first semiconductor region including a first semiconductor channel having a semiconductor-rich upper surface, while the second semiconductor region includes a second semiconductor channel excluding the semiconductor-rich upper surface,
wherein forming the first semiconductor region further comprises:
forming a first set of spacers extending from the top surface of the first semiconductor channel so as to define a first gate between the first set of spacers, the first gate including a first high-k dielectric layer in contact with the spacers, and a first metal gate material in contact with the high-k dielectric layer;
depositing a fist sacrificial material between the first set of spacers, the sacrificial material comprising a combination of the first semiconductor material and an oxide material; and
annealing the first sacrificial material to form the first semiconductor-rich surface on a portion of the top surface of the first semiconductor channel between the first set of spacers.
15. The method of claim 14 , wherein forming the first semiconductor region includes forming is a p-field effect transistor (pFET) region, wherein forming the pFET region further comprises:
forming SiGe material that defines the first semiconductor channel;
depositing the first sacrificial material comprising SiGeOx; and
annealing the first sacrificial material so that the SiGeOx chemically reacts with the SiGe channel to form a Si-rich region on a portion of the top surface of the SiGe material to define the semiconductor-rich surface.
16. The method of claim 15 , wherein forming the second semiconductor region includes forming an n-field effect transistor (nFET) region, wherein forming the nFET region further comprises:
forming Si material that defines the second semiconductor channel; and
forming a second set of spacers extending from the top surface of the Si material so as to define a second gate between the second set of spacers, and
wherein the second gate includes a second high-k dielectric layer in contact with the second set of spacers, and a second metal gate material in contact with the second high-k dielectric layer.
17. The method of claim 16 further comprising forming an ozone layer on the Si-rich layer.
18. The method of claim 17 , further comprising forming the ozone layer between the Si-rich layer and the first high-k dielectric layer.
19. The method of claim 18 further comprising forming an ozone layer on the Si channel between the second set of spacers.
20. The method of claim 19 , further comprising forming the ozone layer between the Si channel and the second high-k dielectric layer.