Vertical transport FETs having a gradient threshold voltage
Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by introducing a threshold voltage modifying dopant into a physically exposed portion of a metal gate layer composed of an n-type workfunction TiN. The threshold voltage modifying dopant changes the threshold voltage of the original metal gate layer.
1. A semiconductor structure comprising:
a vertical transport nFET and a laterally adjacent vertical transport pFET, wherein
the vertical transport nFET comprises:
at least one semiconductor fin present in an nFET device region and extending upwards from a surface of a base semiconductor substrate;
a bottom n-doped source/drain structure located on the base semiconductor substrate and contacting sidewall surfaces of a lower portion of the at least one semiconductor fin, wherein the bottom n-doped source/drain structure serves as a drain region;
a gate dielectric layer located above the bottom n-doped source/drain structure and contacting another portion of the sidewall surfaces of the at least one semiconductor fin;
an nFET gate structure located laterally adjacent a sidewall of the gate dielectric layer, the nFET gate structure comprising a TiN liner having a first threshold voltage and a TiN portion having a second threshold voltage that is greater than the first threshold voltage; and
a top n-doped source/drain structure located on an upper portion of the at least one semiconductor fin and serving a source region; and
the vertical transport pFET comprises:
at least one semiconductor fin present in a pFET device region and extending upwards from the surface of the base semiconductor substrate;
a bottom p-doped source/drain structure located on the base semiconductor substrate and contacting sidewall surfaces of a lower portion of the at least one semiconductor fin, wherein the bottom p-doped source/drain structure serves as a drain region;
a gate dielectric layer located above the bottom p-doped source/drain structure and contacting another portion of the sidewall surfaces of the at least one semiconductor fin;
a pFET gate structure located laterally adjacent a sidewall of the gate dielectric layer, the pFET gate structure comprising a TiN liner having the second threshold voltage and a TiN portion having a third threshold voltage that is greater than the second threshold voltage; and
a top p-doped source/drain structure located on an upper portion of the at least one semiconductor fin and serving as a source region.
2. The semiconductor structure of claim 1 , further comprising a gate encapsulation liner located on the nFET gate structure and the pFET gate structure.
3. The semiconductor structure of claim 2 , further comprising a MOL dielectric structure located adjacent the gate encapsulation liner.
4. The semiconductor structure of claim 1 , further comprising a bottom spacer located between the bottom n-doped source/drain structure and the gate dielectric layer in the nFET device region and between the bottom p-doped source/drain structure and the gate dielectric layer in the pFET device region.
5. The semiconductor structure of claim 4 , further comprising a top spacer located on the MOL dielectric structure.
6. The semiconductor structure of claim 1 , further comprising contact structures contacting surfaces of the top n-doped source/drain structure and the top p-doped source/drain structure.
7. The semiconductor structure of claim 1 , further comprising an isolation structure located between the vertical transport nFET and the vertical transport pFET, wherein the isolation structure has a topmost surface that is coplanar with a topmost surface of bottom n-doped source/drain structure and a topmost surface of the bottom p-doped source/drain structure.
8. The semiconductor structure of claim 1 , wherein the least one semiconductor fin present in the nFET device region has a same height as the least one semiconductor fin present in the pFET device region.
9. The semiconductor structure of claim 1 , wherein the first threshold voltage of the TiN liner in the nFET device region is from 4.3 eV to 4.6 eV and the second threshold voltage of the TiN portion in the nFET device region is from 4.6 eV to 4.9 eV.
10. The semiconductor structure of claim 9 , wherein the second threshold voltage of the TiN liner in the pFET device region is from 4.6 eV to 4.9 eV and the third threshold voltage of the TiN portion in the pFET device region is from 4.4 eV to 4.7 eV.
11. The semiconductor structure of claim 1 , wherein the TiN portion having the second threshold voltage in the nFET device region and the TiN liner in the pFET device region are composed of TiN that contains a threshold voltage modifying dopant in a dopant concentration of from 1.5E20 atoms/cm 3 to 8E21 atoms/cm 3 .
12. The semiconductor structure of claim 11 , wherein the threshold voltage modifying dopant is fluorine or oxygen.
13. The semiconductor structure of claim 1 , wherein the TiN portion having the third threshold voltage in the pFET device region is composed of TiN that includes a threshold voltage modifying dopant in a dopant concentration from 1.E20 atoms/cm 3 to 8E21 atoms/cm 3 .
14. The semiconductor structure of claim 13 , wherein the threshold voltage modifying dopant is fluorine or oxygen.
15. The semiconductor structure of claim 5 , further comprising an interlayer dielectric material located on the MOL dielectric structure.
16. The semiconductor structure of claim 15 , further comprising a first contact structure located in the interlayer dielectric material and contacting a surface of the top n-doped source/drain structure, and a second contact structure located in the interlayer dielectric material and contacting a surface of the top p-doped source/drain structure.
17. The semiconductor structure of claim 1 , wherein the top n-doped source/drain structure has a faceted shape and the top p-doped source/drain structure has a faceted shape.
18. The semiconductor structure of claim 1 , wherein the top n-doped source/drain structure has a diamond shape and the top p-doped source/drain structure has a diamond shape.
19. The semiconductor structure of claim 1 , wherein the top n-doped source/drain structure contacts a topmost surface and a sidewall surface of the least one semiconductor fin present in the nFET device region, and the top p-doped source/drain structure contacts a topmost surface and a sidewall surface of the least one semiconductor fin present in the pFET device region.
20. The semiconductor structure of claim 9 , wherein the TiN liner in the nFET device region is composed entirely of TiN.