FINFETS WITH CONTROLLABLE AND ADJUSTABLE CHANNEL DOPING
A method of forming features of a finFET structure includes forming fins on a surface of a substrate. A first liner is formed around each fin and a shallow trench isolation region is formed around each fin. A dopant layer is implanted in each fin. A portion of the shallow trench isolation region is etched from each fin. A first portion of the structure is blocked and the first liner replaced with a second liner in a second portion of the structure.
1 . A finFET structure, comprising:
a plurality of fins located on a surface of a substrate;
a first liner disposed around each fin in a high threshold voltage region of the structure, with a dopant layer implanted into each fin; and
a second liner disposed around each fin in a low threshold voltage region of the structure, with a dopant layer implanted into each fin;
wherein the first liner and the second liner comprise different materials.
2 . The finFET structure of claim 1 , wherein the first liner comprises a material selected from nitride, nitride oxide, or a combination comprising at least one of the foregoing.
3 . The finFET structure of claim 2 , wherein the first liner comprises a nitride.
4 . The finFET structure of claim 1 , wherein the second liner comprises an oxide.
5 . The finFET structure of claim 4 , wherein the second liner comprises silicon dioxide.
6 . The finFET structure of claim 1 , wherein an upper portion of the fins in the first region comprise a substantially low concentration dopants from the dopant layer.
7 . The finFET structure of claim 1 , wherein the second liner is used to control and adjust channel doping for the fin.
8 . The finFET structure of claim 1 , wherein the second liner is formed onto the structure with by a method selected from chemical vapor deposition, plasma deposition, physical vapor deposition, atomic layer deposition or a combination comprising at least one of the foregoing.
9 . The finFET structure of claim 8 , wherein the method is plasma enhanced chemical vapor deposition.
10 . The finFET structure of claim 1 , wherein the first portion comprises a high threshold voltage region of the structure.
11 . The finFET structure of claim 1 , wherein the second portion comprises a low threshold voltage region of the structure.
12 . The finFET structure of claim 1 , wherein a hardmask layer is present in the plurality of fins located on the surface of the substrate.
13 . The finFET structure of claim 12 , wherein the hardmask layer comprises nitride.
14 . The finFET structure of claim 12 , wherein the hardmask layer comprises silicon oxide, silicon nitride, SiOCN, SiBCN, or a combination thereof.
15 . The finFET structure of claim 1 , further comprising a shallow trench isolation on the first liner.
16 . The finFET structure of claim 1 , further comprising a dummy gate and spacers.
17 . The finFET structure of claim 1 , wherein a source/drain epitaxy region is present in the finFET structure.
18 . The finFET structure of claim 15 , further comprising a replacement metal gate after removal of the dummy gate.
19 . The finFET structure of claim 6 , wherein the concentration of dopants is less than or equal to 1.×10 17 /(cm 3 ).
20 . The finFET structure of claim 1 , wherein the substrate comprises silicon, silicon carbide, germanium, silicon germanium, silicon germanium carbon, gallium arsenide, indium arsenide, indium phosphide, aluminum arsenide, cadmium selenide, cadmium sulfide, cadmium telluride, zinc oxide, zinc selenide, zinc sulfide, zinc telluride, or a combination thereof.