Fin-type FET with low source or drain contact resistance
Embodiments of the invention are directed to methods of forming a FinFET. A non-limiting example method includes forming a fin across from a major surface of a substrate. A dummy gate is formed around a channel region of the fin. A source region or a drain region is formed on the fin, and the dummy gate is replaced with a metal gate structure. Subsequent to replacing the dummy gate with the metal gate structure, dopants are inserted into the source region or the drain region.
1. A method of forming a fin-type field effect transistor (FinFET), the method comprising:
forming a fin across from a major surface of a first region of a substrate having the first region and a second region;
forming a dummy gate around a channel region of the fin;
forming a first interlayer dielectric (ILD) over the first region, wherein the first ILD comprises a first dielectric material;
forming a second ILD over the second region, wherein the second ILD comprises a second dielectric material that is different from the first dielectric material;
removing the first ILD from over the first region;
forming a source region or a drain region on the fin;
replacing the dummy gate with a metal gate structure; and
subsequent to replacing the dummy gate with the metal gate structure, inserting dopants into the source region or the drain region.
2. The method of claim 1 , wherein replacing the dummy gate with the metal gate structure comprises an annealing operation.
3. The method of claim 1 further comprising, subsequent to replacing the dummy gate with the metal gate structure, performing a re-crystallization operation on the source region or the drain region.
4. The method of claim 1 , wherein the fin comprises silicon (Si).
5. The method of claim 1 , wherein the fin comprises silicon germanium (SiGe).
6. The method of claim 1 , wherein the dopants comprise n-type dopants.
7. The method of claim 1 , wherein the dopants comprise p-type dopants.
8. A method of forming fin-type field effect transistors (FinFETs), the method comprising:
forming a substrate comprising a major surface having a first region and a second region;
forming a first fin across from the first region of the major surface of the substrate;
forming a second fin across from the second region of the major surface of the substrate;
forming a first interlayer dielectric (ILD) over the first region, wherein the first ILD comprises a first dielectric material;
forming a second source region or a second drain region on the second fin;
forming a second ILD over the second region, wherein the second ILD comprises a second dielectric material that is different from the first dielectric material;
removing the first ILD from over the first region;
forming a first source region or a first drain region on the first fin;
forming a first dummy gate around a first channel region of the first fin;
forming a second dummy gate around a second channel region of the second fin;
replacing the first dummy gate with a first metal gate structure; and
replacing the second dummy gate with a second metal gate structure.
9. The method of claim 8 further comprising, subsequent to replacing the first dummy gate with the first metal gate structure, removing the first ILD and inserting first dopants into the first source region or the first drain region.
10. The method of claim 9 further comprising, subsequent to replacing the second dummy gate with the second metal gate structure, replacing the first ILD with a third ILD, removing the second ILD, and inserting second dopants into the second source region or the second drain region.
11. The method of claim 8 further comprising forming a first sidewall spacer along a first sidewall of the first dummy gate.
12. The method of claim 11 further comprising forming a second sidewall spacer along a second sidewall of the second dummy gate.
13. The method of claim 12 , wherein a thickness dimension of the first sidewall spacer is approximately equal to a thickness dimension of the second sidewall spacer.
14. The method of claim 12 , wherein the first sidewall spacer and the second sidewall spacer are formed by the same operation.
15. The method of claim 8 , wherein:
replacing the first dummy gate with the first metal gate structure comprises an annealing operation; and
replacing the second dummy gate with the second metal gate structure comprising another annealing operation.
16. The method of claim 8 further comprising:
subsequent to replacing the first dummy gate with the first metal gate structure, performing a first re-crystallization operation on the first source region or the first drain region; and
subsequent to replacing the second dummy gate with the second metal gate structure, performing a second re-crystallization operation on the second source region or the second drain region.
17. The method of claim 8 , wherein the second fin comprises silicon (Si).
18. The method of claim 8 , wherein the first fin comprises silicon germanium (SiGe).
19. The method of claim 10 , wherein:
the dopants of the first source region or the first drain region comprise n-type dopants; and
the dopants of the second source region or the second drain region comprise p-type dopants.