FIN-TYPE FET WITH LOW SOURCE OR DRAIN CONTACT RESISTANCE
Embodiments of the invention are directed to methods of forming a FinFET. A non-limiting example method includes forming a fin across from a major surface of a substrate. A dummy gate is formed around a channel region of the fin. A source region or a drain region is formed on the fin, and the dummy gate is replaced with a metal gate structure. Subsequent to replacing the dummy gate with the metal gate structure, dopants are inserted into the source region or the drain region.
1 .- 19 . (canceled)
20 . A configuration of fin-type field effect transistors (FinFETs) comprising:
a substrate comprising a major surface having an NFET region and a PFET region;
a first fin across from the NFET region of the major surface of the substrate;
a second fin across from the PFET region of the major surface of the substrate;
a first metal gate around a first channel region of the first fin;
a second metal gate around a second channel region of the second fin;
a second doped source region or a second doped drain region on the second fin;
a first doped source region or a first doped drain region on the first fin;
a layer of sidewall spacer material in the NFET region and the PFET region;
wherein a first segment of the layer of the sidewall spacer material is along a first sidewall of the first metal gate;
wherein a second segment of the layer of the sidewall spacer material is along a second sidewall of the second metal gate;
wherein a thickness dimension of the layer of sidewall spacer material is substantially uniform and extends through first segment of the layer of sidewall spacer material and the second segment of the layer of sidewall spacer material.