IP Library Granted Patent US 10,615,083
Granted Patent B2
US 10,615,083 · App. 16/266,469 · Granted Apr 7, 2020

Formation of common interfacial layer on Si/SiGe dual channel complementary metal oxide semiconductor device

Inventors: Ruqiang Bao (Wappingers Falls, NY); Hemanth Jagannathan (Niskayuna, NY); ChoongHyun Lee (Rensselaer, NY); Shogo Mochizuki (Clifton Park, NY)
Assignee: International Business Machines Corporation
H01L21/823857H01L21/31122H01L21/823807H01L27/092
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Quick Facts
Patent No.
US 10,615,083
App. No.
16/266,469
Granted
Apr 7, 2020
Kind
B2
Abstract

A method is presented for forming a semiconductor structure. The method includes forming a silicon (Si) channel for a first device, forming a first interfacial layer over the Si channel, forming a silicon-germanium (SiGe) channel for a second device, forming a second interfacial layer over the SiGe channel, and selectively removing germanium oxide (GeO X ) from the second interfacial layer by applying a combination of hydrogen (H 2 ) and hydrogen chloride (HCl). The second interfacial is silicon germanium oxide (SiGeO X ) and removal of the GeO X results in formation of a pure silicon dioxide (SiO 2 ) layer.

Claims (30)

1. A semiconductor structure comprising:

a first channel formed for a first device;

a first interfacial layer disposed over the first channel;

a second channel formed for a second device; and

a second interfacial layer disposed over the second channel;

wherein germanium oxide (GeO X ) is selectively removed from the second interfacial layer by applying a combination of gases to convert the first interfacial layer to have a same chemical compound as the second interfacial layer and a high-k metal gate is then disposed in direct contact with the converted first interfacial layer.

2. The structure of claim 1 , wherein the first device is an n-type field effect transistor (nFET).

3. The structure of claim 1 , wherein the second device is a p-type field effect transistor (pFET).

4. The structure of claim 1 , wherein the first channel is silicon (Si), the second channel is silicon germanium (SiGe), and the second interfacial is silicon germanium oxide (SiGeO X ).

5. The structure of claim 1 , wherein removal of the GeO X results in formation of a pure silicon dioxide (SiO 2 ) layer.

6. The structure of claim 1 , wherein the converted first interfacial layer is formed between spacers.

7. The structure of claim 6 , wherein the combination of gases are applied to sidewalls of the spacers before the converted first interfacial layer is formed.

8. The structure of claim 1 , wherein removal of the GeO X prevents breaking of Si—O bonds in the second interfacial layer.

9. The structure of claim 1 , wherein removal of the GeO X results in decreased interface trap density in the second interfacial and the second channel.

10. The structure of claim 1 , wherein the gases are a combination of hydrogen (H 2 ) and hydrogen chloride (HCl).

11. A semiconductor structure comprising:

a first channel formed for a first device;

a first interfacial layer disposed in direct contact with the first channel;

a second channel formed for a second device; and

a second interfacial layer disposed in direct contact with the second channel, the second interfacial layer constructed from a different material than the first interfacial layer;

wherein germanium oxide (GeO X ) is selectively removed from the second interfacial layer by applying a combination of gases to convert the first interfacial layer to have a same chemical compound as the second interfacial layer.

12. The structure of claim 11 , wherein a high-k metal gate is disposed in direct contact with the converted first interfacial layer.

13. The structure of claim 11 , wherein the first channel is silicon (Si), the second channel is silicon germanium (SiGe), and the second interfacial is silicon germanium oxide (SiGeO X ).

14. The structure of claim 11 , wherein removal of the GeO X results in formation of a pure silicon dioxide (SiO 2 ) layer.

15. The structure of claim 11 , wherein the converted first interfacial layer is formed between spacers.

16. The structure of claim 11 , wherein the combination of gases are applied to sidewalls of the spacers before the converted first interfacial layer is formed.

17. The structure of claim 11 , wherein removal of the GeO X prevents breaking of Si—O bonds in the second interfacial layer.

18. The structure of claim 11 , wherein removal of the GeO X results in decreased interface trap density in the second interfacial and the second channel.

19. The structure of claim 11 , wherein the gases are a combination of hydrogen (H 2 ) and hydrogen chloride (HCl).

20. The structure of claim 11 , wherein the first device is an n-type field effect transistor (nFET) and the second device is a p-type field effect transistor (pFET).

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052557/0327 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2019
From: BAO, RUQIANG; JAGANNATHAN, HEMANTH; LEE, CHOONGHYUN; MOCHIZUKI, SHOGO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 048230/0509 →
Continuity (2)
Division 15412499 · Jan 23, 2017
Related Publication 20190181052A1 · Jun 13, 2019
Cited By (1)
US 12,568,683