Porous silicon relaxation medium for dislocation free CMOS devices
A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
1. A method for forming complementary metal oxide semiconductor devices, the method comprising:
doping a second portion of a tensile-strained silicon layer outside a first portion to form a doped portion;
growing an undoped silicon layer on the doped portion; and
relaxing strain in the undoped silicon layer over the doped portion by converting the doped portion to an oxide to form a relaxed layer.
2. The method as recited in claim 1 , further comprising growing a SiGe layer on the relaxed layer.
3. The method as recited in claim 2 , further comprising oxidizing the SiGe layer to convert the relaxed layer to a compressed SiGe layer.
4. The method as recited in claim 3 , further comprising etching fins from the tensile-strained silicon layer and the compressed SiGe layer.
5. The method as recited in claim 4 , wherein doping the second portion of the tensile-strained silicon layer includes boron doping the second portion.
6. The method as recited in claim 5 , wherein converting the doped portion to an oxide to form a relaxed layer includes converting the doped portion to a porous silicon then converting the porous silicon to the oxide.
7. The method as recited in claim 6 , wherein converting the doped portion to a porous silicon includes converting the doped portion to the porous silicon with a porosity of at least 50%.
8. The method as recited in claim 7 , wherein oxidizing the SiGe layer to convert the relaxed silicon layer to a compressed SiGe layer includes employing a condensation process to form the compressed SiGe layer.
9. The method as recited in claim 8 , further comprising forming N-type field effect transistors from the fins formed from the tensile-strained silicon layer.
10. The method as recited in claim 9 , further comprising forming P-type field effect transistors from the fins formed from the compressed SiGe layer.
11. The method as recited in claim 10 , wherein the N-type field effect transistors and the P-type field effect transistors have different heights and the method further comprises adjusting the heights to adjust N/P ratio.
12. The method as recited in claim 11 , wherein relaxing strain in the undoped silicon layer includes relaxing strain by at least 50%.
13. The method as recited in claim 12 , wherein converting the doped portion to a porous silicon to form a relaxed silicon layer includes anodizing the doped portion.
14. A method for forming complementary metal oxide semiconductor devices, the method comprising:
etching a second portion of a tensile-strained silicon layer outside a first portion using a hard mask;
doping the second portion of the tensile-strained silicon layer outside the first portion;
growing an undoped silicon layer on the doped portion; and
relaxing strain in the undoped silicon layer over the doped portion by converting the doped portion to an oxide to form a relaxed layer.
15. The method as recited in claim 14 , further comprising growing a SiGe layer on the relaxed layer.
16. The method as recited in claim 15 , further comprising oxidizing the SiGe layer to convert the relaxed layer to a compressed SiGe layer.
17. The method as recited in claim 16 , further comprising etching fins from the tensile-strained silicon layer and the compressed SiGe layer.
18. The method as recited in claim 17 , wherein doping the second portion of the tensile-strained silicon layer includes boron doping the second portion.
19. The method as recited in claim 18 , wherein converting the doped portion to an oxide to form a relaxed layer includes converting the doped portion to a porous silicon then converting the porous silicon to the oxide.
20. The method as recited in claim 19 , wherein converting the doped portion to a porous silicon includes converting the doped portion to the porous silicon with a porosity of at least 50%.