SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES
A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.
1 . A method, comprising:
forming an active device on a semiconductor layer on a buried oxide layer;
forming a shallow trench isolation structure on the buried oxide layer and adjacent to the semiconductor layer, wherein a top surface of the shallow trench isolation structure is higher than a top surface of the semiconductor layer; and
forming a passive structure on the top surface of the shallow trench isolation structure.
2 . The method of claim 1 , further comprising forming a liner between the shallow trench isolation structure and the buried oxide layer.
3 . The method of claim 2 , wherein the liner is between the shallow trench isolation structure and the semiconductor layer.
4 . The method of claim 1 , wherein the active device comprises a stacked structure.
5 . The method of claim 4 , wherein the stacked structure comprises: a high-k dielectric material; a metal gate; and a semiconductor material.
6 . The method of claim 4 , wherein the stacked structure comprises:
a high-k dielectric material on the semiconductor layer;
a metal gate on the high-k dielectric material; and
a semiconductor material on the metal gate.
7 . The method of claim 1 , further comprising forming an insulator layer over the active device and the passive structure.
8 . The method of claim 7 , wherein the insulator layer contacts sidewalls of the active device.
9 . The method of claim 7 , wherein the insulator layer contacts the top surface of the semiconductor layer.
10 . The method of claim 7 , wherein the insulator layer contacts the top surface of the shallow trench isolation structure.
11 . The method of claim 7 , wherein the insulator layer contacts each of:
sidewalls of the active device;
the top surface of the semiconductor layer; and
the top surface of the shallow trench isolation structure.