Post passivation interconnection process and structures
View Patent ↗A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.
1. An integrated circuit comprising:
a silicon substrate;
a transistor in or on said silicon substrate;
a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a dielectric layer between said first and second metal layers;
a separating layer over said first metallization structure and said dielectric layer, wherein said separating layer comprises a nitride, wherein a first opening in said separating layer is over a first contact point of said first metallization structure, and said first contact point is at a bottom of said first opening;
a first polymer layer over said separating layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers;
a second metallization structure on said first polymer layer, wherein said second metallization structure is connected to said first contact point through said first opening and a second opening in said first polymer layer, wherein said second metallization structure comprises a glue layer and an electroplated copper layer over said glue layer, wherein an undercut has an edge of said glue layer recessed from an edge of said electroplated copper layer; and
a second polymer layer on said second metallization structure.
2. The integrated circuit of claim 1 , wherein said first polymer layer comprises polyimide.
3. The integrated circuit of claim 1 , wherein said second metallization structure further comprises a copper seed layer between said glue layer and said electroplated copper layer.
4. The integrated circuit of claim 1 , wherein said glue layer comprises titanium.
5. The integrated circuit of claim 1 , wherein said glue layer comprises titanium nitride.
6. The integrated circuit of claim 1 , wherein said glue layer comprises a titanium-tungsten alloy.
7. The integrated circuit of claim 1 , wherein a third opening in said separating layer is over a second contact point of said first metallization structure, and said second contact point is at a bottom of said third opening, wherein said second metallization structure is connected to said second contact point through said third opening and a fourth opening in said first polymer layer, wherein said first contact point is connected to said second contact point through said second metallization structure.
8. The integrated circuit of claim 1 , wherein said second metallization structure further comprises a nickel layer on said electroplated copper layer.
9. The integrated circuit of claim 8 , wherein said nickel layer has a thickness between 0.1 and 3 micrometers.
10. The integrated circuit of claim 1 , wherein said electroplated copper layer has a thickness between 3 and 20 micrometers.