Structure of MTCMOS cell
View Patent ↗An architecture of the layout of the MTCMOS standard cell designed for low power consumption is supplemented so that the pick-up cells are included in the power line of the MTCMOS cell. Therefore, when the logic circuit is constructed using the library layout of the MTCMOS cell in which the related pick-up cells are not included, pick-up cells consisting of only the ends of the pick-up cells are not needed every 50 μm during the placement of the MTCMOS standard cell. The flexibility of the cell placement may thereby be improved. In addition, since additional space for the pick-up cells is not required, the size of the MTCMOS may be reduced, saving space on the semiconductor substrate.
1. An apparatus comprising:
an n-well and a p-well formed in an active region over a semiconductor substrate;
a p-type transistor formed in the n-well region and an n-type transistor formed in the p-well region;
a first metal wiring line connecting a drain of the p-type transistor and a source of the n-type transistor to each other;
an n+ pick-up cell connected to the first metal wiring line in a region adjacent to a drain of the p-type transistor; and
a p+ pick-up cell connected to the first metal wiring line in a region adjacent to the source of the n-type transistor.
2. The apparatus of claim 1 , comprising a second metal wiring line, to be used as a power line, connected to the first metal wiring line through vias.
3. The apparatus of claim 2 , wherein the n+ and p+ pick-up cells are formed in a power line region of a multi-threshold complimentary metal oxide semiconductor cell where the first and second metal wiring lines are formed.
4. The apparatus of claim 1 , wherein the n+ and p+ pick-up cells are bone-shaped.