Semiconductor wafer and manufacturing method for semiconductor device
View Patent ↗A semiconductor wafer and a manufacturing method for a semiconductor device are provided, which prevent peeling-off of films and pattern skipping in a wafer edge portion. A silicone substrate has formed thereon gate structures in active regions isolated by a trench isolation film; a contact interlayer film; and a multilayer interconnection structure formed by alternate laminations of low-k via interlayer films, i.e., V layers, and low-k interconnect interlayer films, i.e., M layers. In a Fine layer ranging from first to fifth interlayer films, the M layers are removed from the wafer edge portion, but the V layers are not removed therefrom. Further, the contact interlayer film is not removed from the wafer edge portion.
1. A manufacturing method for a semiconductor device, comprising:
(a) providing a semiconductor substrate;
(b) forming a plurality of gate structures on the semiconductor substrate;
(c) forming a first interlayer film to cover the semiconductor substrate and the gate structures;
(d) forming a first wiring layer over the first interlayer film, the first wiring layer including sub-steps of:
(d-1) forming a first layer including a second interlayer film with a dielectric constant of 3.0 or lower and a via;
(d-2) after step (d-1), forming a second layer including a third interlayer film with a dielectric constant of 3.0 or lower and a wire; and
(e) after step (d), forming at least one of upper wiring layers over the first wiring layer, each of the upper wiring layers being formed by performing the same step as step (d), wherein
the first interlayer film and the second interlayer film are not removed from a wafer edge portion of the semiconductor substrate, and
the third interlayer film is removed in a given width from the wafer edge portion of the semiconductor substrate.
2. The manufacturing method for a semiconductor device according to claim 1 , wherein in step (d), the wiring layer is formed by a dual damascene process.
3. The manufacturing method for a semiconductor device according to claim 1 , wherein
a width of the third interlayer film removed in the upper wiring layer is different from the given width of the third interlayer film in the first wiring layer.
4. The manufacturing method for a semiconductor device according to claim 3 , wherein
the third interlayer film includes a plurality of films.
5. The manufacturing method for a semiconductor device according to claim 1 , further comprising:
forming an isolation film on the semiconductor substrate to isolate said plurality of gate structures, wherein
in step (b), the plurality of gate structures are not formed on an area of said semiconductor substrate where the third interlayer film is removed.
6. A manufacturing method for a semiconductor device, comprising:
(a) providing a semiconductor substrate;
(b) forming a plurality of gate structures on the semiconductor substrate;
(c) forming a first interlayer film to cover the semiconductor substrate and the gate structures;
(d) forming a first wiring layer over the first interlayer film, the first wiring layer including a sub-step of:
(d-1) forming a first layer including a second interlayer film with a dielectric constant of 3.0 or lower and a via;
(d-2) after step (d-1), forming a second layer including a third interlayer film with a dielectric constant of 3.0 or lower and a wire; and
(e) after step (d), forming at least one of upper wiring layers over the first wiring layer, each of the upper wiring layers being formed by performing the same step as step (d), wherein
the first interlayer film and the second interlayer film are arranged on a wafer edge portion of the semiconductor substrate, and
the third interlayer film is removed in a given width from the wafer edge portion of the semiconductor substrate.
7. The manufacturing method for a semiconductor device according to claim 6 , wherein in step (d), the wiring layer is formed by a dual damascene process.
8. The manufacturing method for a semiconductor device according to claim 6 , wherein
a width of the third interlayer film removed in the upper wiring layer is different from the given width of the third interlayer film in the first wiring layer.
9. The manufacturing method for a semiconductor device according to claim 8 , wherein
the third interlayer film includes a plurality of films.
10. The manufacturing method for a semiconductor device according to claim 6 , further comprising:
forming an isolation film on the semiconductor substrate to isolate said plurality of gate structures, wherein
in step (b), the plurality of gate structures are not formed on an area of said semiconductor substrate where the third interlayer film is removed.