Transformer data coupler with high common mode immunity
A data coupler includes a transformer having primary and secondary windings, a data transmitter coupled to the primary winding of the transformer, and a data receiver coupled to the secondary winding. The data transmitter includes a first driver and a second driver having outputs coupled to respective ends of the primary winding. The first driver is responsive to a data signal and the second driver is responsive to a delayed version of the data signal, such that the primary winding is supplied with pulses representing a difference between the data signal and the delayed version of the data signal. The data coupler also includes an ac (alternating current) path to ground from the secondary winding for conducting to ground common mode signals coupled to the secondary winding via an inter-winding capacitance of the transformer.
1. A data coupler comprising:
a transformer having primary and secondary windings;
a data transmitter, coupled to the primary winding of the transformer and comprising a first driver and a second driver having outputs coupled to respective ends of the primary winding, the first driver being responsive to a data signal and the second driver being responsive to a delayed version of the data signal, such that the primary winding is supplied with pulses representing a difference between the data signal and the delayed version of the data signal;
a data receiver coupled to the secondary winding; and
an ac (alternating current) path to ground from the secondary winding for conducting to ground common mode signals coupled to the secondary winding via an inter-winding capacitance of the transformer.
2. A data coupler as claimed in claim 1 wherein the transformer has a primary to secondary turns ratio of N:1 where N is a number greater than one; said ac path to ground is coupled to one end of the secondary winding, whereby common mode currents in the first driver and the second driver are unequal; and the first driver and the second driver are scaled with a ratio (N−1):(N+1) to substantially equalize voltage drops in the first driver and the second driver due to the unequal common mode currents.
3. A data coupler as claimed in claim 2 wherein each of the first driver and the second driver comprises a CMOS (complementary metal oxide semiconductor) output stage.
4. A data coupler as claimed in claim 2 further comprising a resistor coupled between the secondary winding and an input of the data receiver, wherein the resistor and an input capacitance of the data receiver form a low pass filter.
5. A data coupler as claimed in claim 2 wherein the data receiver comprises two comparators each arranged to compare a signal derived from an input of the data receiver with a respective threshold level, and a flip-flop arranged to be set and cleared by respective outputs of the comparators to determine the data signal at an output of the flip-flop.
6. A data coupler as claimed in claim 2 wherein the delayed version of the data signal is delayed relative to the data signal by less than about 1 μs.
7. A data coupler as claimed in claim 2 wherein the delayed version of the data signal is delayed relative to the data signal by less than about 200 ns.
8. A data coupler as claimed in claim 1 wherein the delayed version of the data signal is delayed relative to the data signal by less than about 1 μs.
9. A data coupler as claimed in claim 1 wherein the secondary winding has a center tap coupled to ground, wherein the ac path to ground includes the center tap coupled to ground, the secondary winding having two ends coupled to respective inputs of the data receiver via respective low pass filters.
10. A data coupler as claimed in claim 1 wherein the outputs of the first driver and the second driver are coupled to the respective ends of the primary winding via respective capacitors.