Wafer level interconnection of inverted metamorphic multijunction solar cells
View Patent ↗A method of forming a plurality of discrete, interconnected solar cells mounted on a carrier by providing a first semiconductor substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell structure; forming a metal back contact layer over the solar cell structure; mounting a carrier on top of the metal back contact; removing the first substrate; and lithographically patterning and etching the solar cell structure to form a plurality of discrete solar cells mounted on the carrier.
1. A method of forming a plurality of discrete solar cells mounted on a carrier comprising:
providing a first semiconductor substrate;
depositing on said first substrate a sequence of layers of semiconductor material forming a solar cell structure;
forming a metal back contact layer over the solar cell structure;
mounting said carrier on top of the metal back contact layer;
removing the first substrate; and
lithographically patterning and etching said solar cell structure to form said plurality of discrete solar cells mounted on said carrier.
2. The method as defined in claim 1 , wherein the sequence of layers of semiconductor material forms a triple junction solar cell, including top, middle and bottom solar subcells.
3. The method as defined in claim 1 , wherein the mounting step includes adhering the solar cell structure to the carrier.
4. The method as defined in claim 1 , wherein the carrier is selected from the group of Ge, GaAs, and silicon.
5. The method as defined in claim 1 , wherein the solar cell structure is bonded to said carrier by an adhesive.
6. The method as defined in claim 1 , wherein the carrier is electrically insulating and the solar cell structure is eutectically bonded to the carrier.
7. The method as defined in claim 1 , further comprising thinning the carrier to a predetermined thickness.
8. The method as defined in claim 1 further comprising interconnecting the discrete solar cells mounted on the carrier by discrete conductors.
9. The method as defined in claim 8 , wherein the discrete conductors are wire bonds.
10. The method as defined in claim 8 , wherein the discrete conductors are film traces.
11. The method as defined in claim 8 , wherein the conductors extend from a front contact on one solar cell to a back contact on another solar cell.
12. The method as defined in claim 1 , wherein the solar cell structure includes layers forming a bypass diode.
13. The method as defined in claim 12 , wherein the solar cell structure is lithographically patterned and etched to form said plurality of discrete solar cells and said bypass diode.
14. The method as defined in claim 13 , further comprising connecting said plurality of discrete solar cells and said bypass diode in parallel.
15. The method as defined in claim 14 , wherein connecting said plurality of discrete solar cells and said bypass diode is performed by welding, soldering or wire bonding.
16. A method as defined in claim 1 , wherein said depositing a sequence of layers comprises:
forming an upper first solar subcell on said first substrate having a first band gap;
forming a middle second solar subcell over said upper first solar subcell having a second band gap smaller than said first band gap;
forming a graded interlayer having a third band gap over said middle second solar subcell; and
forming a lower third solar subcell over said graded interlayer having a fourth band gap smaller than said second band gap such that said lower third solar subcell is lattice mismatched with respect to said middle second solar subcell.
17. The method as defined in claim 16 , wherein said third band gap of said graded interlayer is greater than said second band gap.
18. The method as defined in claim 16 , wherein said upper first solar subcell is composed of InGa(Al)P.
19. The method as defined in claim 16 , wherein said middle second solar subcell is composed of a GaAs, GaInP, GaInAs, GaAsSb, or GaInAsN emitter region and a GaAs, GaInAs, GaAsSb, or GaInAsN base region.
20. The method as defined in claim 16 , wherein said lower third solar subcell is composed of an InGaAs base and emitter layer, or a InGaAs base layer and a InGaP emitter layer.
21. The method as defined in claim 16 , wherein the graded interlayer is compositionally graded to lattice match said middle second solar subcell on one side and said lower third solar subcell on the other side.
22. The method as defined in claim 16 , wherein the graded interlayer is composed of InGaAlAs.
23. The method as defined in claim 16 , wherein the graded interlayer has approximately a 1.5 eV band gap throughout its thickness.
24. The method as defined in claim 16 , wherein the graded interlayer is composed of any of the As, N, Sb based III-V compound semiconductors subject to the constraints of having the in-plane lattice parameter greater or equal to that of said middle second solar subcell and less than or equal to that of said lower third solar subcell, and having a band gap energy greater than that of said middle second solar subcell.
25. The method as defined in claim 16 , wherein said graded interlayer is composed of nine or more steps of layers of semiconductor material with monotonically changing lattice constant and constant band gap.
26. The method as defined in claim 1 , further comprising:
patterning said metal back contact layer into a grid; and
etching a trough around the periphery of said discrete solar cells so as to form a plurality of mesa structures on said carrier.
27. A method as defined in claim 20 , further comprising thinning the carrier and mounting said discrete solar cells on a support.
28. A method of manufacturing an array of interconnected solar cells comprising:
providing a first semiconductor substrate;
depositing on said first semiconductor substrate a sequence of layers of semiconductor material forming a solar cell;
depositing a sequence of layers of semiconductor material forming a bypass diode on said first semiconductor substrate;
mounting a carrier on top of the sequence of layers;
forming a plurality of discrete solar cells from said sequence of layers; and
electrically interconnecting said solar cells.
29. The method as defined in claim 28 , wherein the interconnecting step includes forming a wire bond between the discrete solar cells.
30. A method of manufacturing an array of interconnected solar cells comprising:
providing a first semiconductor substrate;
depositing on said first semiconductor substrate a sequence of layers of semiconductor material forming a solar cell;
mounting a carrier on top of the sequence of layers;
forming a plurality of discrete solar cells from said sequence of layers; and
electrically interconnecting said solar cells,
wherein the interconnecting step includes depositing a conductive layer between the discrete solar cells.
31. The method as defined in claim 30 , wherein the conductive layer extends from a front contact on one solar cell to a back contact on an adjacent solar cell.
32. The method as defined in claim 28 , further comprising electrically interconnecting the discrete solar cells and the bypass diode in a parallel electrical circuit.
33. The method as defined in claim 32 , wherein the interconnecting step includes depositing a conductive layer between the solar cell and the corresponding bypass diode.
34. The method as defined in claim 28 , wherein the sequence of layers of semiconductor material forms a triple junction solar cell, including top, middle and bottom solar subcells.
35. The method as defined in claim 28 , wherein the mounting step includes adhering the solar cell to the carrier.
36. The method as defined in claim 28 , wherein the carrier is selected from the group of sapphire, Ge, GaAs, or silicon.
37. The method as defined in claim 36 , wherein the solar cell is bonded to said carrier by an adhesive.
38. The method as defined in claim 28 , wherein the carrier is electrically insulating and the solar cell is eutectically bonded to the carrier.
39. The method as defined in claim 28 , further comprising thinning the carrier to a predetermined thickness.
40. The method as defined in claim 28 , further comprising:
mounting the solar cell on a rigid coverglass; and
removing the carrier.
41. A method as defined in claim 34 , wherein said middle and bottom subcells are lattice mismatched.
42. A method as defined in claim 34 , further comprising a graded interlayer disposed between said middle and bottom subcells, and having a band gap greater than the band gap of said middle subcell.
43. A method as defined in claim 42 , wherein said graded interlayer is composed of any of the As, N, Sb based III-V compound semiconductors subject to the constraints of having the in-plane lattice parameter greater or equal to that of the middle subcell and less than or equal to that of the bottom subcell.
44. A method as defined in claim 42 , wherein the graded interlayer is composed of (In x Ga 1-x ) y Al 1-y As, with x and y selected such that the band gap of the interlayer remains constant at approximately 1.50 eV.