Semiconductor device using logic chip

1. A system-in-package type semiconductor device comprising: a logic chip; and a memory chip connected with external terminal through said logic chip, wherein said logic chip

comprises a data holding circuit configured to hold a test data in a test mode,

stores the test data supplied through a data input/output terminal in said data holding circuit in response to a test data set command, and

writes the test data which has been stored in said data holding circuit in said memory chip in response to a test data write command,

wherein the data holding circuit is configured to only hold data to be written in said memory chip,

wherein said logic chip reads the test data stored in said memory chip as a read test data in response to a test data read command, and outputs the read test data through said data input/output terminal,

wherein said data holding circuit comprises a plurality of registers, which hold a plurality of the test data corresponding to different test patterns, and

wherein said data holding circuit comprises a selector which selects one of said plurality of registers in response to a register selection instruction externally supplied from said logic chip.

2. The system-in-package type semiconductor device according to claim 1 , wherein said logic chip comprises:

a data setting circuit configured to supply the test data to said data holding circuit;

a data write circuit configured to supply the test data stored in said data holding circuit to said memory chip; and

a data read circuit configured to read the test data having stored in said memory chip,

said data setting circuit comprises:

a logical AND circuit configured to output a clock signal in response to the test data set command; and

a first switch configured to connect said data input/output terminal and said data holding circuit.

3. The system-in-package type semiconductor device according to claim 2 , wherein said data write circuit comprises:

a second switch configured to connect said data holding circuit and said memory chip.

4. The system-in-package type semiconductor device according to claim 3 , wherein said data read circuit comprises:

a data comparing circuit configured to compare the read test data and the test data stored in said data holding circuit,

said data comparing circuit comprises:

an exclusive OR circuit configured to execute an EXOR calculation of the read test data and an expectation data read from said data holding circuit in response to said test data read command, and

the execution result of the EXOR calculation is outputted through said data input/output terminal.

5. The system-in-package type semiconductor device according to claim 1 , wherein the data holding circuit is configured to hold data only in the test mode.

6. A logic chip comprising:

a data holding circuit configured to hold a test data in a test mode;

a data setting circuit configured to supply the test data to said data holding circuit;

a data write circuit configured to supply the test data stored in said data holding circuit to a memory chip,

wherein said data setting circuit stores the test data supplied through a data input/output terminal in said data holding circuit in response to a test data set command,

wherein said data write circuit writes said test data stored in said data holding circuit in the memory chip in response to a test data write command,

wherein said data holding circuit is configured to only hold data to be written in the memory chip,

wherein said logic chip reads the test data stored in said memory chip as a read test data in response to a test data read command, and outputs the read test data through said data input/output terminal,

wherein said data holding circuit comprises a plurality of registers, which hold a plurality of the test data corresponding to different test patterns, and

wherein said data holding circuit comprises a selector which selects one of said plurality of registers in response to a register selection instruction externally supplied from said logic chip.

7. The logic chip according to claim 6 , further comprising:

a data read circuit configured to read the test data stored in said memory chip,

wherein said data read circuit reads the test data stored in said memory chip as a read test data in response to a test data read command, and compares the read test data and the test data stored in said data holding circuit.

8. The logic chip according to claim 6 , wherein said data holding circuit is configured to hold data only in the test mode.