IP Library Granted Patent US 7,579,667
Granted Patent B2
US 7,579,667 · App. 12/191,035 · Granted Aug 25, 2009

Bonded-wafer superjunction semiconductor device

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Quick Facts
Patent No.
US 7,579,667
App. No.
12/191,035
Granted
Aug 25, 2009
Kind
B2
Abstract

A bonded-wafer semiconductor device includes a semiconductor substrate, a buried oxide layer disposed on a first main surface of the semiconductor substrate and a multi-layer device stack. The multi-layer device stack includes a first device layer of a first conductivity disposed on the buried oxide layer, a second device layer of a second conductivity disposed on the first device layer, a third device layer of the first conductivity disposed on the second device layer and a fourth device layer of the second conductivity disposed on the third device layer. A trench is formed in the multi-layer device stack. A mesa is defined by the trench. The mesa has first and second sidewalls. A first anode/cathode layer is disposed on a first sidewall of the multi-layer device stack, and a second anode/cathode layer is disposed on the second sidewall of the multi-layer device stack.

Claims (22)

1. A bonded-wafer semiconductor device comprising:

a semiconductor substrate having first and second main surfaces opposite to each other;

a buried oxide layer disposed on at least a portion of the first main surface of the semiconductor substrate;

a multi-layer device stack having a first main surface and a second main surface, the multi-layer device stack including:

a first device layer of a first conductivity disposed on the buried oxide layer;

a second device layer of a second conductivity opposite to the first conductivity disposed on the first device layer;

a third device layer of the first conductivity disposed on the second device layer; and

a fourth device layer of the second conductivity disposed on the third device layer;

at least one trench formed in the first main surface of the multi-layer device stack, the at least one trench extending to a first depth position in the multi-layer device stack;

at least one mesa proximate the first main surface of the multi-layer device stack being defined by the at least one trench, the at least one mesa having a first sidewall and a second sidewall opposite the first sidewall;

a first anode/cathode layer disposed on a first sidewall of the multi-layer device stack; and

a second anode/cathode layer disposed on the second sidewall of the multi-layer device stack.

2. The bonded-wafer semiconductor device according to claim 1 , wherein the multi-layer device stack further includes:

a fifth device layer of the first conductivity disposed on the fourth device layer; and

a sixth device layer of the second conductivity disposed on the fifth device layer.

3. The bonded-wafer semiconductor device according to claim 2 , wherein the multi-layer device stack further includes:

a seventh device layer of the first conductivity disposed on the sixth device layer; and

an eighth device layer of the second conductivity disposed on the seventh device layer.

4. The bonded-wafer semiconductor device according to claim 1 , further comprising:

a heavily doped layer disposed on the second sidewall of the multi-layer device stack.

5. The bonded-wafer semiconductor device according to claim 1 , wherein a lateral Schottky diode is formed between the first and second anode/cathode layers through the multi-layer device stack.

6. The bonded-wafer semiconductor device according to claim 1 , wherein the first and second anode/cathode layers are formed of one or more of aluminum Al, aluminum silicon Al[% Si], copper Cu, gold Au, silver Ag, titanium Ti, tungsten W, nickel Ni, undoped polysilicon, doped polysilicon and combinations thereof.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2009
From: ICEMOS TECHNOLOGY CORPORATION
To: ICEMOS TECHNOLOGY LTD.
Reel/Frame 022076/0237 →