Patent Assignment
Reel/Frame 022076/0237
Assignment of Assignor's Interest
Recorded: 2009-01-08
Received: 2009-01-08
Pages: 12
Assignor
ICEMOS TECHNOLOGY CORPORATION
Executed: 2008-09-17
Assignee
ICEMOS TECHNOLOGY LTD.
5 HANNAHSTOWN HILL, BELFAST, GBX, BT17 0LT, UNITED KINGDOM
Covered Properties
(57)
Reinforcement Module for a Motor Vehicle Body
Application:
12/297,046 →
Method for Managing Electric Power Within a Powertrain System
Application:
12/243,106 →
Vehicle Subsystem Control Method and Apparatus
Application:
12/293,418 →
Torsion-Beam Rear Axle of a Vehicle
Application:
12/207,336 →
Technique for Stable Processing of Thin/Fragile Substrates
Application:
12/203,995 →
Photodetector Array Using Isolation Diffusions as Crosstalk Inhibitors Between Adjacent Photodiodes
Application:
12/204,371 →
Silicon Wafer Having Through-Wafer Vias
Application:
12/202,638 →
Bonded-Wafer Superjunction Semiconductor Device
Application:
12/191,035 →
Front Lip Pin/Nip Diode Having a Continuous Anode/Cathode
Application:
12/175,586 →
Photodetector Array Using Isolation Diffusions as Crosstalk Inhibitors Between Adjacent Photodiodes
Application:
12/142,185 →
Front Side Electrical Contact for Photodetector Array and Method of Making Same
Application:
12/116,638 →
Positive-Intrinsic-Negative (Pin)/Negative-Intrinsic-Positive (Nip) Diode
Application:
12/116,286 →
Methods for Manufacturing a Trench Type Semiconductor Device Having a Thermally Sensitive Refill Material
PCT:
PCTUS2008061139 ↗
Bonded Wafer Substrate for Use in Mems Structures
Application:
61/040,210 →
Multi-Directional Trenching of a Plurality of Dies in Manufacturing Superjunction Devices
Application:
12/031,909 →
Multi-Directional Trenching of a Die in Manufacturing Superjunction Devices
Application:
12/031,895 →
Trench Depth Monitor for Semiconductor Manufacturing
Application:
61/028,321 →
Multi-Angle Rotation for Ion Implantation of Trenches in Superjunction Devices
Application:
61/028,215 →
Methods for Manufacturing a Trench Type Semiconductor Device Having a Thermally Sensitive Refill Material
Application:
12/029,857 →
Superjunction Device Having a Dielectric Termination and Methods for Manufacturing the Device
Application:
61/020,540 →
Superjunction Devices Having Narrow Surface Layout of Terminal Structures and Methods of Manufacturing the Devices
PCT:
PCTUS2007089048 ↗
Methods for Manufacturing a Trench Type Semiconductor Device Having a Thermally Sensitive Refill Material
Application:
11/962,523 →
PCT:
PCTUS2007089036 ↗
Superjunction Devices Having Narrow Surface Layout of Terminal Structures and Methods of Manufacturing the Devices
Application:
11/962,530 →
Silicon Wafer Having Through-Wafer Vias With A Predetermined Geometric Shape
Application:
11/925,329 →
Multi-Directional Trenching in Manufacturing Superjuction Devices
Application:
60/975,878 →
Semiconductor Devices with Sealed, Unlined Trenches and Methods of Forming Same
Application:
11/838,359 →
PCT:
PCTUS2007075810 ↗
Method of Manufacturing a Photodiode Array with Through-Wafer Vias
Application:
11/837,150 →
PCT:
PCTUS2007075613 ↗
Varying Pitch Adapter and a Method of Forming a Varying Pitch Adapter
Application:
11/772,104 →
PCT:
PCTUS2007015253 ↗
Superjunction Devices Having Narrow Surface Layout of Terminal Structures and Methods of Manufacturing the Devices
Application:
60/915,939 →
Technique for Stable Processing of Thin/Fragile Substrates
PCT:
PCTUS2007067640 ↗
Methods for Manufacturing a Trench Type Semiconductor Device Having a Thermally Sensitive Refill Material
Application:
60/913,425 →
Methods for Manufacturing a Trench Type Semiconductor Device Having a Thermally Sensitive Refill Material
Application:
60/913,432 →
Front Side Electrical Contact for Photodetector Array and Method of Making Same
Application:
11/681,543 →
Photodiode Having Increased Proportion of Light-Sensitive Area to Light-Insensitive Area
Application:
11/681,576 →
Technique for Stable Processing of Thin/Fragile Substrates
Application:
11/675,407 →
Backlit Photodiode and Method of Manufacturing a Backlit Photodiode
Application:
11/609,934 →
Front Lit Pin/Nip Diode Having a Continuous Anode/Cathode
Application:
11/554,437 →
Photodetector Array Using Isolation Diffusions as Crosstalk Inhibitors Between Adjacent Photodiodes
Application:
11/548,546 →
Bonded-Wafer Superjunction Semiconductor Device
Application:
11/466,132 →
Semiconductor Devices With Sealed, Unlined Trenches and Methods of Forming Same
Application:
60/822,263 →
Semiconductor Devices With Sealed, Unlined Trenches and Methods of Forming Same
Application:
60/822,261 →
Positive-Intrinsic-Negative (Pin) / Negative-Intrinsic-Positive (Nip) Diode
Application:
11/463,613 →
Method of Manufacturing a Photodiode Array with Through-Wafer Vias
Application:
60/821,993 →
Varying Pitch Adapter and a Method of Forming a Varying Pitch Adapter
Application:
60/806,150 →
Superjunction Device Having Oxide Lined Trenches and Method for Manufacturing a Superjunction Device Having Oxide Lined Trenches
Application:
10/596,720 →
Silicon Wafer Having Through-Wafer Vias
Application:
11/381,605 →
PCT:
PCTUS2006017024 ↗
Technique for Stable Processing of Thin/Fragile Substrates
Application:
11/380,457 →
Superjunction Device Having Oxide Lined Trenches and Method for Manufacturing a Superjunction Device Having Oxide Lined Trenches
PCT:
PCTUS2006015310 ↗
Front side electrical contact for photodetector array and method of making same
Application:
60/778,481 →
Photodiode having increased proportion of light-sensitive area to light-insensitive area
Application:
60/778,480 →
Backlit photodiode and method of manufacturing a backlit photodiode
Application:
60/750,873 →
Front lit PIN/NIP diode having a continuous anode/cathode
Application:
60/731,171 →
Detector array using isolation diffusions as crosstalk inhibitors between adjacent pixels
Application:
60/725,876 →
Bonded-wafer superjunction semiconductor device
Application:
60/710,234 →
Positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode
Application:
60/706,918 →
Silicon wafer having through-wafer vias
Application:
60/677,510 →
Superjunction device having oxide lined trenches and method for manufacturing a superjunction device having oxide lined trenches
Application:
60/673,935 →