Silicon wafer having through-wafer vias
View Patent ↗A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. A trench is formed in the semiconductor substrate at the first main surface. The trench extends to a first depth position in the semiconductor substrate. The trench is lined with the dielectric material. The trench is filled with a conductive material. An electrical component is electrically connected to the conductive material exposed at the first main surface. A cap is mounted to the first main surface. The cap encloses the electrical component and the electrical connection.
1. A method of manufacturing a semiconductor device comprising:
providing a semiconductor substrate having first and second main surfaces opposite to each other;
forming in the semiconductor substrate at least one trench in the first main surface, the at least one trench extending to a first depth position in the semiconductor substrate, the at least one trench defining a perimeter boundary around a portion of the semiconductor substrate, the portion of semiconductor substrate bounded by the at least one trench forming a conductive via;
lining the at least one trench with a dielectric material;
filling the at least one trench with one of an insulating material and a semi-insulating material;
electrically connecting an electrical component to the conductive via at the first main surface; and
mounting a cap to the first main surface, the cap enclosing at least a portion of the electrical component and the electrical connection between the electrical component and the conductive via.
2. The method according to claim 1 , wherein the filling of the at least one trench is with at least one of undoped polysilicon, doped polysilicon, doped oxide, undoped oxide, silicon nitride and semi-insulating polycrystalline silicon (SIPOS).
3. The method according to claim 1 , wherein the at least one trench is formed utilizing micro-electro-mechanical systems (MEMS) technology to machine the semiconductor substrate.
4. The method according to claim 1 , wherein the dielectric material is deposited using one of low pressure (LP) chemical vapor deposition (CVD) Tetraethylorthosilicate (TEOS) and a spun-on-glass (SOG) deposition.
5. The method according to claim 1 , wherein the planarizing is performed by chemical mechanical polishing (CMP).
6. The method according to claim 1 , wherein the electrical component is one of an accelerometer, a gyroscope, a rate sensor, a pressure sensor, a resonator, a temperature sensor, and an optical sensor.
7. The method according to claim 1 , wherein the perimeter boundary is generally one of circular, triangular, rectangular, elliptical, polygonal and non-geometric/asymmetrical.
8. The method according to claim 1 , further comprising:
lining at least a portion of the first main surface surrounding the at least one trench with a dielectric material.
9. The method according to claim 1 , further comprising:
planarizing the first main surface.
10. The method according to claim 1 , further comprising:
exposing at least a portion of the conductive via.
11. The method according to claim 1 , further comprising:
planarizing the second main surface to expose the conductive via at the second main surface.