IP Library Patent Application 12191861
Patent Application
App. No. 12/191,861

SOI SUBSTRATES AND DEVICES ON SOI SUBSTRATES HAVING A SILICON NITRIDE DIFFUSION INHIBITION LAYER AND METHODS FOR FABRICATING

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Patent No.
US None
App. No.
12/191,861
Abstract

Semiconductor-on-insulator substrates and methods for fabricating semiconductor-on-insulator substrates are provided. One exemplary method comprises providing a first silicon-comprising substrate, providing a second silicon-comprising substrate, forming a first silicon nitride layer overlying the second silicon-comprising substrate, and coupling the first silicon-comprising substrate to the second silicon-comprising substrate such that the first silicon nitride layer is interposed between the two substrates.

Claims (37)

1 . A method for fabricating a silicon-on-insulator substrate, the method comprising the steps of:

providing a first silicon-comprising substrate;

providing a second silicon-comprising substrate;

depositing a first silicon nitride layer overlying the second silicon-comprising substrate by a low-pressure chemical vapor deposition (LPCVD) process;

forming a first silicon oxide layer overlying the first silicon nitride layer;

forming a second silicon oxide layer overlying and in contact with the first silicon-comprising substrate; and

bonding the second silicon oxide layer and the first silicon oxide layer together to form a buried oxide layer that couples the first silicon-comprising substrate to the second silicon-comprising substrate such that the first silicon nitride layer is interposed between the buried oxide layer and the second silicon-comprising substrate.

2 . The method of claim 1 , further comprising the step of thinning the second silicon-comprising substrate.

3 . The method of claim 2 , wherein the step of thinning the second silicon-comprising substrate comprises the steps of:

implanting hydrogen ions to create a stressed region within the second silicon-comprising substrate; and

cleaving the second silicon-comprising substrate in the stressed region.

4 . (canceled)

5 . The method of claim 4 , wherein the step of coupling comprises bonding the first silicon oxide layer and the first silicon-comprising substrate together.

6 . (canceled)

7 . The method of claim 1 , wherein the step of bonding is performed using a pressure and heat treatment:

8 . The method of claim 1 , wherein the step of coupling comprises bonding the first silicon nitride layer and the first silicon-comprising substrate together.

9 . The method of claim 1 , further comprising the step of forming a second silicon nitride layer overlying the first silicon-comprising substrate and wherein the step of coupling comprises bonding the first silicon nitride layer and the second silicon nitride layer together.

10 . The method of claim 9 , further comprising the step of forming a silicon oxide layer overlying the first silicon-comprising substrate before the step of forming a second silicon nitride layer.

11 . The method of claim 1 , wherein the step of forming a first silicon nitride layer comprises forming a silicon nitride layer having a thickness in a range of about from 0.1 nm to 30 nm.

12 . (canceled)

13 . A method for fabricating a semiconductor device, the method comprising the steps of:

providing a first silicon-comprising substrate;

providing a second silicon-comprising substrate;

forming a first silicon nitride layer overlying the first silicon-comprising substrate;

coupling the first silicon-comprising substrate to the second silicon-comprising substrate with the first silicon nitride layer interposed therebetween;

thinning the first silicon-comprising substrate;

forming a gate stack overlying the first silicon-comprising substrate; and

implanting impurity dopant ions into the first silicon-comprising substrate using the gate stack as an implantation mask.

14 . The method of claim 13 , wherein the step of coupling further comprises forming a second silicon nitride layer interposed between the first silicon nitride layer and the second silicon-comprising substrate.

15 . The method of claim 13 , wherein the step of coupling further comprises forming a first silicon oxide layer interposed between the second silicon-comprising substrate and the first silicon nitride layer.

16 . The method of claim 15 , wherein the step of coupling further comprises forming a second silicon oxide layer interposed between the first silicon oxide layer and the first silicon nitride layer.

17 . The method of claim 15 , wherein the step of coupling further comprises forming a second silicon nitride layer interposed between the first silicon oxide layer and the first silicon nitride layer.

18 . The method of claim 13 , wherein the step of forming a first silicon nitride layer comprises forming a first silicon nitride layer using an LPCVD process.

19 . The method of claim 13 , wherein the step of forming a first silicon nitride layer comprises forming a first silicon nitride layer having a thickness in a range of from about 0.1 nm to 30 nm.

20 . (canceled)

21 . The method of claim 1 , wherein the first silicon nitride layer overlies the buried oxide layer.

22 . The method of claim 21 , wherein the first silicon nitride layer is formed in contact with the buried oxide layer and wherein the buried oxide layer directly contacts the first silicon-comprising substrate.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
AFFIRMATION OF PATENT ASSIGNMENT Recorded Aug 18, 2009
From: ADVANCED MICRO DEVICES, INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 023120/0426 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2008
From: MAITRA, KINGSUK; KERBER, ANDREAS
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 021392/0430 →