Method and apparatus for increasing operating frequency of a system for testing electronic devices
View Patent ↗A test system includes a communications channel that terminals in a probe, which contacts an input terminal of an electronic device to be tested. A resistor is connected between the communications channel near the probe and ground. The resistor reduces the input resistance of the terminal and thereby reduces the rise and fall times of the input terminal. The channel may be terminated in a branch having multiple paths in which each path is terminated with a probe for contacting a terminal on electronic devices to be tested. Isolation resistors are included in the branches to prevent a fault at one input terminal from propagating to the other input terminals. A shunt resistor is provided in each branch, which reduces the input resistance of the terminal and thereby reduces the rise and fall times of the input terminal. The shunt resistor may also be sized to reduce, minimize, or eliminate signal reflections back up the channel.
1. An apparatus for interfacing test signals between a tester and an electronic device under test, said apparatus comprising:
a structure;
a plurality of channel terminals disposed on said structure and configured to connect electrically with communications channels from said tester;
a plurality of probes disposed on said structure and configured to contact test features of said electronic device;
a plurality of electrically conductive paths, each of said conductive paths connecting a first one of said channel terminals with a set of one or more of said probes, wherein the one or more of said probes in each said set are exclusive to said set;
a power supply path connected to a second one of said channel terminals different from said first one of said channel terminals, said power supply path defining a voltage potential; and
a plurality of shunt resistors disposed on said structure, each of said shunt resistors electrically connected between one of said probes and said voltage potential.
2. The apparatus of claim 1 , wherein said structure comprises a first substrate on which said probes are disposed.
3. The apparatus of claim 2 , wherein said shunt resistors are disposed on said first substrate.
4. The apparatus of claim 3 , wherein said shunt resistors are thin film resistors.
5. The apparatus of claim 3 , wherein said probes and said shunt resistors are disposed on a first surface of said first substrate.
6. The apparatus of claim 3 , wherein said shunt resistors are disposed within said first substrate.
7. The apparatus of claim 2 , wherein said structure further comprises a second substrate on which said channel terminals are disposed.
8. The apparatus of claim 2 further comprising a switch wherein said shunt resistors are electrically connected to said voltage potential through said switch.
9. The apparatus of claim 8 , wherein said switch is disposed on said structure.
10. The apparatus of claim 2 , wherein said voltage potential is ground.
11. The apparatus of claim 2 , wherein said structure is a probe card assembly.
12. The apparatus of claim 2 , wherein said shunt resistors have a resistance such that a total resistance of said shunt resistors in parallel with input resistance of said test features is substantially equal to an impedance of said electrically conductive paths.
13. The apparatus of claim 1 , further comprising a plurality of series resistors wherein said series resistors are disposed in each of said plurality of electrically conductive paths between said channel terminals and said probes.
14. A method of testing an electronic device comprising a plurality of input terminals, said method comprising:
obtaining a test system comprising:
a structure,
a plurality of channel terminals disposed on said structure and configured to connect electrically with drive channels from a tester,
a plurality of probes disposed on said structure and configured to contact said input terminals of said electronic device,
a plurality of electrically conductive paths, each of said conductive paths connecting a first one of said channel terminals with a set of one or more of said probes, wherein said one or more of said probes in each said set are exclusive to said set,
a power supply path connected to a second one of said channel terminals different from said first one of said channel terminals, said power supply path defining a voltage potential, and
a plurality of shunt resistors disposed on said structure, each of said shunt resistors electrically connected between one of said probes and said voltage potential;
bringing said probes into contact with said input terminals of said electronic device; and
performing functional tests through said drive channels on said electronic device.
15. The method of claim 14 , further comprising increasing magnitude of a voltage applied by said drive channels to compensate for voltage drop caused by said shunt resistor.
16. The method of claim 14 further comprising:
disconnecting said shunt resistors from said first ones of said drive channels via a switch; and
performing parametric tests through said drive channels on said electronic device.
17. The method of claim 14 , wherein resistance values of said shunt resistors are selected to decrease rise times of said input terminals.
18. The method of claim 14 , wherein resistance values of said shunt resistors are selected to decrease fall times of said input terminals.
19. The method of claim 14 , wherein said first ones of said drive channels each comprise a series resistor.
20. A method of testing an electronic device comprising a plurality of inputs, said method comprising:
obtaining a test system comprising a plurality of drive channels terminating in probes, first ones of said drive channels comprising a shunt resistor, wherein said shunt resistors are located proximate to said probes and are electrically connected between said first ones of said drive channels and a voltage potential defined by second ones of said drive channels, wherein said second ones of said drive channels correspond to power supply channels and are different than said first ones of said drive channels, wherein said voltage potential corresponds to ground; bringing said probes into contact with said input terminals of said electronic device; and
performing functional tests through said drive channels on said electronic device.
21. A method of testing an electronic device comprising a plurality of inputs, said method comprising:
providing a test system comprising a plurality of drive channels terminating in probes, first ones of said drive channels comprising a shunt resistor, wherein said shunt resistors are located proximate to said probes and are electrically connected between said first ones of said drive channels and a voltage potential defined by second ones of said drive channels;
bringing said probes into contact with said input terminals of said electronic device; and
performing functional tests through said drive channels on said electronic device, wherein resistance of said shunt resistors are selected so that a parallel resistance of said shunt resistors and input resistance of said input terminals is substantially equal to an impedance of said first ones of said drive channels.
22. An apparatus for interfacing test signals between a tester and an electronic device under test, said apparatus comprising:
a structure comprising a substrate;
a plurality of channel terminals disposed on said structure and configured to connect electrically with communications channels from said tester;
a plurality of probes disposed on said substrate and configured to contact test features of said electronic device;
a plurality of electrically conductive paths connecting ones of said channel terminals with ones of said probes, wherein ones of said electrically conductive paths correspond to a ground potential;
a plurality of shunt resistors disposed on said structure, each of said shunt resistors electrically connected between one of said electrically conductive paths and said ground potential; and
a plurality of switches wherein said shunt resistors are electrically connected to said ground potential through said switch.
23. The apparatus of claim 22 , wherein said plurality of switches are disposed on said structure.