Gain amplifier having switched-capacitor structure for minimizing settling time
View Patent ↗Provided is a gain amplifier having a switched-capacitor structure capable of minimizing settling time, in which an input capacitor is connected to an input terminal during a first clock sampling an input signal, and thus an output terminal of the amplifier is reset in advance to an estimated output voltage value rather than 0 by the input capacitor. Accordingly, the slight move of the output terminal of the amplifier is sufficient to settle to a desired value in an amplification mode, so that slewing time can be reduced, and as a result, overall settling time and power consumption can be minimized.
1. A gain amplifier having a switched-capacitor structure for minimizing settling time, comprising:
a first switch to which an input voltage is applied from an input terminal;
a sampling capacitor for storing the input voltage at a first clock;
an N-stage amplifier for amplifying and outputting the input signal stored in the sampling capacitor at a second clock that does not overlap the first clock, wherein N denotes an integer of 2 or greater;
second and third switches for applying a common mode voltage to the N-stage amplifier;
a feedback capacitor connected between an input and an output of the N-stage amplifier;
an input capacitor connected at one side to the input terminal;
a fourth switch for connecting the other side of the input capacitor between an N−1th amplifier and an Nth amplifier of the N-stage amplifier at the first clock; and
a fifth switch for connecting the N−1th amplifier of the N-stage amplifier to the Nth amplifier at the second clock.
2. The gain amplifier of claim 1 , further comprising a parasitic capacitor connected between the N−1th and Nth capacitors of the N-stage amplifier and ground.
3. The gain amplifier of claim 1 , wherein at the first clock, an output voltage of the N-stage amplifier is reset to an estimated output voltage value, according to the input voltage, by the input capacitor.
4. The gain amplifier of claim 3 , wherein the estimated output voltage value V OUT according to the input voltage is represented by the following equation:
V OUT =−A 2 *V T2 =A 2 *V IN *C I /( C I +C P )
wherein V IN denotes an input voltage, C P denotes a value of a parasitic capacitor, C I denotes a value of an input capacitor, and −A2 denotes a gain value of an Nth amplifier of the N-stage amplifier.
5. The gain amplifier of claim 1 , further comprising:
a miller capacitor for compensating for a frequency of the N-stage amplifier; and
a sixth switch for connecting the miller capacitor between an input and an output of the Nth amplifier of the N-stage amplifier at the second clock.
6. The gain amplifier of claim 1 , further comprising an amplifier having a gain of −1 connected between the input terminal and the input capacitor.