Filter circuit and communication semiconductor device using the same
View Patent ↗The present invention intends to provide a filter circuit in which an area occupied by the circuit can be reduced by suppressing the scale of its circuit configuration while a predetermined vicinity disturbance wave rejection ratio is maintained and a communication semiconductor device using the same, the filter circuit filtering an analog signal and including a voltage/current conversion circuit for converting the analog signal from voltage to current, and a capacitor array which executes signal processing by charging/discharging the current converted by the voltage/current conversion circuit to/from plural capacitors, the capacitor array being so constructed that the plural capacitors are divided to plural stages so that signals averaged by the capacitor on a preceding stage are accumulated in the capacitor on a next stage successively.
1. A filter circuit for filtering an analog signal, comprising:
a voltage/current conversion circuit for converting said analog signal from voltage to current; and
a capacitor array which executes signal processing by charging or discharging said current converted by said voltage/current conversion circuit to/from plural capacitors,
wherein said capacitor array is so constructed that said plural capacitors are divided to plural stages to accumulate signals averaged by a capacitor on a preceding stage in a capacitor on a next stage successively.
2. The filter circuit according to claim 1 , wherein said capacitor array comprises: a first switching element for controlling the charge or discharge of each of said capacitors; a second switching element for resetting each of said capacitors; and a third switching element for averaging each of said capacitors on each stage.
3. The filter circuit according to claim 2 , wherein said capacitor array is so constructed that at a timing when said third switching element on a preceding stage is opened, said first switching element of said capacitor on a next stage is opened and before the timing, said second switching element of said capacitor on the next stage resets said capacitor on the next stage.
4. A communication semiconductor device, comprising:
an amplifier circuit which amplifies an analog signal received by an antenna at a predetermined amplification factor;
a frequency conversion circuit which converts said analog signal outputted from said amplifier circuit to a predetermined frequency;
a filter circuit which allows a signal desired to be received to pass through, of said analog signals converted in terms of the frequency by said frequency conversion circuit;
an AD conversion circuit which converts the signal passing through said filter circuit to digital signal; and
an arithmetic operation circuit which executes a predetermined signal processing on the signal converted to the digital signal by the AD conversion circuit, wherein
said filer circuit is a filter circuit for filtering said analog signal, including a voltage/current conversion circuit for converting said analog signal from voltage to current, and
a capacity array which executes a signal processing by charging or discharging said current converted by said voltage/current conversion circuit to/from plural capacitors,
said capacitor array being so constructed that said plural capacitors are divided to plural stages so that signals averaged by a capacitor on a preceding stage are accumulated in a capacitor on a next stage successively.
5. The communication semiconductor device according to claim 4 , wherein said capacitor array comprises: a first switching element for controlling the charge or discharge of each of said capacitors; a second switching element for resetting each of said capacitors; and a third switching element for averaging each of said capacitors on each stage.
6. The communication semiconductor device according to claim 5 , wherein said capacitor array is so constructed that at a timing when said third switching element on a preceding stage is opened, said first switching element of said capacitor on a next stage is opened and before the timing, said second switching element of said capacitor on the next stage resets said capacitor on the next stage.