Output control signal generating circuit
View Patent ↗An output control signal generating circuit includes latch circuits that are connected in cascade, and a timing signal generating circuit that generates a timing signal to be supplied to the latch circuits, based on a second clock of which phase is advanced from the phase of a first clock used to take in a read command. The timing signal generating circuit delays the phase of a timing signal to be supplied to a relatively pre-stage latch circuit included in the latch circuits, from the phase of a timing signal to be supplied to a relatively latter stage latch circuit included in the latch circuits. With this arrangement, a latch margin of a first latch circuit does not depend on the cycle of an external clock. Accordingly, even when a clock has a very high speed, the output can be controlled correctly.
1. A synchronous dynamic random access memory comprising:
a delay locked loop circuit receiving an external clock to generate an internal clock, and
a CAS latency setting circuit including a first circuit taking in a read command in synchronism with a first active edge of said external clock and outputting an internal command and a second circuit taking in said internal command in synchronism with a second active edge of said internal clock, associated with or linked to said first active edge.
2. The synchronous dynamic random access memory according to claim 1 , wherein
said memory has an n CAS latency, where n is a natural number, and said CAS latency setting circuit outputs a control signal delayed n cycles of said external clock from said read command.
3. A synchronous dynamic random access memory comprising:
a delay locked loop circuit receiving an external clock to generate an internal clock, and
a CAS latency setting circuit including a first circuit taking in a read command in synchronism with a first active edge of said external clock and outputting an internal command and a second circuit taking in said internal command in synchronism with a second active edge, of said internal clock, associated with or linked to said first active edge.
4. The synchronous dynamic random access memory according to claim 3 , wherein
said memory has an n CAS latency, where n is a natural number, and said CAS latency setting circuit outputs a control signal delayed n cycles of said external clock from said read command.
5. The synchronous dynamic random access memory according to claim 4 , wherein
said internal clock has a phase advanced from the phase of said external clock.
6. A synchronous dynamic random access memory device operating in synchronism with an external clock signal and responding to an external command to output a data signal when a predetermined time period defined as a CAS latency has been elapsed, the memory device comprising:
a DLL (Delayed Locked Loop) circuit receiving the external clock signal and producing an internal clock signal;
a plurality of latch circuits each having an input node, an output node and a clock node, the latch circuits being coupled in series to one another such that the output node of a preceding one of the latch circuits is connected to the input node of a succeeding one of the latch circuits, a first one of the latch circuits being supplied at the input node thereof with an internal command signal responsive to the external command, a last one of the latch circuits producing at the output node thereof a control signal corresponding to the CAS latency; and
a plurality of delay circuits each connected between the clock nodes of associated adjacent ones of the latch circuits, the last one of the latch circuits being supplied at the clock node thereof with the internal clock signal from the DLL circuit.
7. The memory device as claimed in claim 6 , wherein the internal clock signal is supplied to the clock node of the last one of the latch circuits through an additional delay circuit.
8. The memory device as claimed in claim 7 , wherein the latch circuits are equal in total number to a sum of the delay circuits and the additional delay circuit.