MEMORY ACCESS CONTROL DEVICE, CONTROL METHOD, AND PROGRAM
A data conversion unit divides data to be written to, for example, a non-volatile memory having a limited number of times of rewriting including erasure of a memory device into divided write data having a predetermined bit width and subjects each of the divided write data to conversion to conversion data in which the update frequency from bit 0 to bit 1 when incrementing or decrementing is performed is approximately equal among respective bit positions. A data reverse conversion unit decomposes the data read from the non-volatile memory into divided read data having the predetermined bit width and subjects each of the divided read data to conversion opposite to the conversion of the data conversion unit so as to return the data to the original data.
1 . A memory access control device comprising:
a memory that has a limited number of times of rewriting;
a data conversion unit that decomposes data to be written to the memory into divided write data having a predetermined bit width and subjects each of the decomposed write data to conversion to conversion data in which the frequency of update from bit 0 to bit 1 when incrementing or decrementing is performed is approximately equal among respective bit positions; and
a data reverse conversion unit that decomposes the data read from the memory into divided read data having the predetermined bit width and subjects each of the divided read data to conversion opposite to the conversion of the data conversion unit so as to return the data to original data.
2 . The memory access control device according to claim 1 , wherein
the data conversion unit decomposes the data to be written to the memory into divided write data having a 2-bit width, 4-bit width, 5-bit width, 6-bit width, 7-bit width, or 8-bit width and subjects each of the divided write data to conversion to the conversion data in which the frequency of update from bit 0 to bit 1 when incrementing or decrementing is performed is approximately equal among respective bit positions; and
the data reverse conversion unit decomposes the data read from the memory into divided read data having the 2-bit width, 4-bit width, 5-bit width, 6-bit width, 7-bit width, or 8-bit width and subjects each of the divided read data to the conversion opposite to the conversion of the data conversion unit to return the data to the original data.
3 . The memory access control device according to claim 2 , wherein
the data conversion unit converts the divided write data having 1 at all bits in binary display and having the predetermined bit width (1111 . . . 1) to data having bit 1 at an arbitrary bit position and bit 0 at all the other bit positions.
4 . The memory access control device according to claim 3 , wherein
the data conversion unit converts a bit sequence 11 having the 2-bit width to a bit sequence 01 or 10,
converts a bit sequence 1111 having the 4-bit width to a bit sequence 0001, 0010, 0100, or 1000,
converts a bit sequence 11111 having the 5-bit width to a bit sequence 00001, 00010, 00100, 01000, or 10000,
converts a bit sequence 111111 having the 6-bit width to a bit sequence 000001, 000010, 000100, 001000, 010000, or 100000,
converts a bit sequence 1111111 having the 7-bit width to a bit sequence 0000001, 0000010, 0000100, 0001000, 0010000, 0100000, or 1000000, and
converts a bit sequence 11111111 having the 8-bit width to a bit sequence 00000001, 00000010, 00000100, 00001000, 00010000, 00100000, 01000000, or 10000000.
5 . The memory access control device according to claim 2 , wherein
the data conversion unit decomposes the data to be written to the memory into the divided write data having the 2-bit width and subjects the divided write data to conversion so that
bit sequences before the conversion are 00, 01, 10, 11 and
bit sequences after the conversion are 00, 01, 11, 10
in binary display; and
the data reverse conversion unit decomposes the data read from the memory into the divided read data having the 2-bit width and subjects the divided read data to reverse conversion so that
bit sequences before the reverse conversion are 00, 01, 11, 10 and
bit sequences after the reverse conversion are 00, 01, 10, 11
in binary display.
6 . The memory access control device according to claim 2 , wherein
the data conversion unit decomposes the data to be written to the memory into the divided write data having the 2-bit width and subjects the divided write data to conversion so that
bit sequences before the conversion are 00, 01, 10, 11 and
bit sequences after the conversion are 00, 10, 11, 01
in binary display; and
the data reverse conversion unit decomposes the data read from the memory into the divided read data having the 2-bit width and subjects the divided read data to reverse conversion so that
bit sequences before the reverse conversion are 00, 10, 11, 01 and
bit sequences after the reverse conversion are 00, 01, 10, 11
in binary display.
7 . The memory access control device according to claim 1 , wherein the data conversion unit and the data reverse conversion unit are provided in the memory.
8 . A memory access control method of a memory having a limited number of times of rewriting, comprising:
a data conversion step that decomposes data to be written to the memory into divided write data having a predetermined bit width and subjects each of the decomposed write data to conversion to conversion data in which the frequency of update from bit 0 to bit 1 when incrementing or decrementing is performed is approximately equal among respective bit positions; and
a data reverse conversion step that decomposes the data read from the memory into divided read data having the predetermined bit width and subjects each of the divided read data to conversion opposite to the conversion of the data conversion step so as to return the data to original data.
9 . The memory access control method according to claim 8 , wherein
in the data conversion step, the data to be written to the memory is decomposed into divided write data having a 2-bit width, 4-bit width, 5-bit width, 6-bit width, 7-bit width, or 8-bit width, and each of the divided write data is subjected to conversion to the conversion data in which the frequency of update from bit 0 to bit 1 when incrementing or decrementing is performed is approximately equal among respective bit positions; and,
in the data reverse conversion step, the data read from the memory is decomposed into divided read data having the 2-bit width, 4-bit width, 5-bit width, 6-bit width, 7-bit width, or 8-bit width, and each of the divided read data is subjected to the conversion opposite to the conversion of the data conversion step so as to return the data to the original data.
10 . The memory access control method according to claim 9 , wherein
in the data conversion step, the divided write data having 1 at all bits in binary display and having the predetermined bit width is converted to data having bit 1 at an arbitrary bit position and bit 0 at all the other bit positions.
11 . The memory access control method according to claim 10 , wherein
in the data conversion step,
a bit sequence 11 having the 2-bit width is converted to a bit sequence 01 or 10,
a bit sequence 1111 having the 4-bit width is converted to a bit sequence 0001, 0010, 0100, or 1000,
a bit sequence 11111 having the 5-bit width is converted to a bit sequence 00001, 00010, 00100, 01000, or 10000,
a bit sequence 111111 having the 6-bit width is converted to a bit sequence 000001, 000010, 000100, 001000, 010000, or 100000,
a bit sequence 1111111 having the 7-bit width is converted to a bit sequence 0000001, 0000010, 0000100, 0001000, 0010000, 0100000, or 1000000, and
a bit sequence 11111111 having the 8-bit width is converted to a bit sequence 00000001, 00000010, 00000100, 00001000, 00010000, 00100000, 01000000, or 10000000.
12 . The memory access control method according to claim 9 , wherein
in the data conversion step, the data to be written to the memory is decomposed into the divided write data having the 2-bit width, and the divided write data is subjected to conversion so that
bit sequences before the conversion are 00, 01, 10, 11 and
bit sequences after the conversion are 00, 01, 11, 10
in binary display; and,
in the data reverse conversion step, the data read from the memory is decomposed into the divided read data having the 2-bit width, and the divided read data is subjected to reverse conversion so that
bit sequences before the reverse conversion are 00, 01, 11, 10 and
bit sequences after the reverse conversion are 00, 01, 10, 11
in binary display.
13 . The memory access control method according to claim 9 , wherein
in the data conversion step, the data to be written to the memory is decomposed into the divided write data having the 2-bit width, and the divided write data is subjected to conversion so that
bit sequences before the conversion are 00, 01, 10, 11 and
bit sequences after the conversion are 00, 10, 11, 01
in binary display; and,
in the data reverse conversion step, the data read from the memory is decomposed into the divided read data having the 2-bit width, and the divided read data is subjected to reverse conversion so that
bit sequences before the reverse conversion are 00, 10, 11, 01 and
bit sequences after the reverse conversion are 00, 01, 10, 11
in binary display.
14 . The memory access control method according to claim 9 , wherein
in the data conversion step, the data to be written to the memory is decomposed into the divided write data having the 4-bit width, and the divided write data is subjected to conversion so that
bit sequences before the conversion are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f and
bit sequences after the conversion are 0, 1, 5, d, 9, 8, a, b, 3, 7, f, e, c, 4, 6, 2
in hexadecimal display; and,
in the data reverse conversion step, the data read from the memory is decomposed into the divided read data having the 2-bit width, and the divided read data is subjected to reverse conversion so that
bit sequences before the reverse conversion are 0, 1, 5, d, 9, 8, a, b, 3, 7, f, e, c, 4, 6, 2 and
bit sequences after the reverse conversion are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f
in hexadecimal display.
15 . A computer-readable storage medium which stores a program allowing a computer to execute
a data conversion step that decomposes data to be written to a memory, which is disposed in a computer and has a limited number of times of rewriting, into divided write data having a predetermined bit width and subjects each of the decomposed write data to conversion to conversion data in which the frequency of update from bit 0 to bit 1 when incrementing or decrementing is performed is approximately equal among respective bit positions; and
a data reverse conversion step that decomposes the data read from the memory into divided read data having the predetermined bit width and subjects each of the divided read data to conversion opposite to the conversion of the data conversion step so as to return the data to original data.
16 . The storage medium according to claim 15 , wherein
in the data conversion step, the data to be written to the memory is decomposed into divided write data having a 2-bit width, 4-bit width, 5-bit width, 6-bit width, 7-bit width, or 8-bit width, and each of the divided write data is subjected to conversion to the conversion data in which the frequency of update from bit 0 to bit 1 when incrementing or decrementing is performed is approximately equal among respective bit positions; and,
in the data reverse conversion step, the data read from the memory is decomposed into divided read data having the 2-bit width, 4-bit width, 5-bit width, 6-bit width, 7-bit width, or 8-bit width, and each of the divided read data is subjected to the conversion opposite to the conversion of the data conversion step so as to return the data to the original data.
17 . The storage medium according to claim 16 , wherein
in the data conversion step, the divided write data having 1 at all bits in binary display and having the predetermined bit width is converted to data having bit 1 at an arbitrary bit position and bit 0 at all the other bit positions.
18 . The storage medium according to claim 17 , wherein
in the data conversion step,
a bit sequence 11 having the 2-bit width is converted to a bit sequence 01 or 10,
a bit sequence 1111 having the 4-bit width is converted to a bit sequence 0001, 0010, 0100, or 1000,
a bit sequence 11111 having the 5-bit width is converted to a bit sequence 00001, 00010, 00100, 01000, or 10000,
a bit sequence 111111 having the 6-bit width is converted to a bit sequence 000001, 000010, 000100, 001000, 010000, or 100000,
a bit sequence 1111111 having the 7-bit width is converted to a bit sequence 0000001, 0000010, 0000100, 0001000, 0010000, 0100000, or 1000000, and
a bit sequence 11111111 having the 8-bit width is converted to a bit sequence 00000001, 00000010, 00000100, 00001000, 00010000, 00100000, 01000000, or 10000000.
19 . The storage medium according to claim 16 , wherein
in the data conversion step, the data to be written to the memory is decomposed into the divided write data having the 2-bit width, and the divided write data is subjected to conversion so that
bit sequences before the conversion are 00, 01, 10, 11 and
bit sequences after the conversion are 00, 01, 11, 10
in binary display; and,
in the data reverse conversion step, the data read from the memory is decomposed into the divided read data having the 2-bit width, and the divided read data is subjected to reverse conversion so that
bit sequences before the reverse conversion are 00, 01, 11, 10 and
bit sequences after the reverse conversion are 00, 01, 10, 11
in binary display.
20 . The storage medium according to claim 16 , wherein
in the data conversion step, the data to be written to the memory is decomposed into the divided write data having the 4-bit width, and the divided write data is subjected to conversion so that
bit sequences before the conversion are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f and
bit sequences after the conversion are 0, 1, 5, d, 9, 8, a, b, 3, 7, f, e, c, 4, 6, 2
in hexadecimal display; and,
in the data reverse conversion step, the data read from the memory is decomposed into the divided read data having the 2-bit width, and the divided read data is subjected to reverse conversion so that
bit sequences before the reverse conversion are 0, 1, 5, d, 9, 8, a, b, 3, 7, f, e, c, 4, 6, 2 and
bit sequences after the reverse conversion are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f
in hexadecimal display.