Lead cutter and method of fabricating semiconductor device
View Patent ↗Aimed at stably forming sheared surfaces of leads of semiconductor devices, and at raising ratio of formation of plated layers onto the sheared surfaces of the leads, a lead cutter has a die 106 , and a cutting punch 110 having a cutting edge at least on the surface facing the die, wherein clearance T between the die 106 and the cutting punch 110 is set within the range from not smaller than 2.3% and smaller than 14.0% of the total thickness of the leads to be cut and plated layers formed on the upper and the lower surfaces thereof.
1. A method of fabricating a semiconductor device comprising:
cutting leads of a semiconductor device, each of said leads having plated layers formed on the upper and the lower surfaces thereof, with a lead cutter including a die, and a cutting punch having a cutting edge at least on the surface facing said die,
wherein the clearance between said die and said cutting punch is set within the range from not smaller than 2.3% and smaller than 14.0% of the total thickness of one of the leads to be cut and plated layers formed on the upper and the lower surfaces of said lead.
2. The method of fabricating a semiconductor device as claimed in claim 1 , wherein the thickness of the plated layers formed on the upper and the lower surfaces of each of said leads is respectively 5 μm or smaller.
3. The method of fabricating a semiconductor device as claimed in claim 1 , wherein said plated layers are composed of a lead-free solder.
4. The method of fabricating a semiconductor device as claimed in claim 1 , wherein said plated layers are composed of nickel/gold, nickel/palladium, or nickel/palladium/gold.