IP Library Granted Patent US 7,580,557
Granted Patent B2
US 7,580,557 · App. 12/200,968 · Granted Aug 25, 2009

Method of design analysis of existing integrated circuits

Assignee: Semiconductor Insights Inc.
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Quick Facts
Patent No.
US 7,580,557
App. No.
12/200,968
Granted
Aug 25, 2009
Kind
B2
Abstract

The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

Claims (14)

1. A rigid comparison method of determining whether a possible location of a standard cell in an image of an IC layout is a true high probability match of the standard cell represented by a template comprising:

computing gradients for the template and a possible location from a set of possible locations;

computing a first set of dot products of the gradients;

applying morphological dilation of the first set of dot products to obtain a second set of dot products;

determining order statistics on the second set of dot products; and

determining if the order statistics are below a predefined threshold,

wherein if the order statistics are less than said predefined threshold, the possible location is a true instance of the standard cell.

2. Apparatus for determining whether a possible location of a standard cell in an image of an IC layout is a high probability match of the standard cell represented by a template using a rigid comparison method comprising:

means for computing gradients for the template and a possible location from a set of possible locations;

means for computing a first set of dot products of the gradients;

means for applying morphological dilation of the first set of dot products to obtain a second set of dot products;

means for determining order statistics on the second set of dot products; and

means for determining if the order statistics are below a predefined threshold,

wherein if the order statistics are less than said predefined threshold, the possible location is a high probability match of the standard cell.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2021
From: STELLUS CAPITAL INVESTMENT CORPORATION, AS ADMINISTRATIVE AGENT
To: TECHINSIGHTS INC.
Reel/Frame 058096/0558 →
SECURITY INTEREST Recorded Nov 10, 2021
From: TECHINSIGHTS INC.; VLSI RESEARCH INC.
To: CAPITAL ONE, NATIONAL ASSOCIATION
Reel/Frame 058096/0721 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Aug 16, 2017
From: TECHINSIGHTS INC.
To: STELLUS CAPITAL INVESTMENT CORPORATION, AS ADMINISTRATIVE AGENT
Reel/Frame 043571/0385 →
CHANGE OF NAME Recorded Oct 9, 2014
From: SEMICONDUCTOR INSIGHTS INC.
To: TECHINSIGHTS INC.
Reel/Frame 033941/0692 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2009
From: ZAVADSKY, VYACHESLAV L.; GONT, VAL; KEYES, EDWARD; ABT, JASON; BEGG, STEPHEN
To: SEMICONDUCTOR INSIGHTS INC.
Reel/Frame 023254/0947 →
Continuity (2)
Division 1092979800 · Aug 31, 2004
Related Publication 20080317327A1 · Dec 25, 2008