Semiconductor device and method of fabricating the same
View Patent ↗A semiconductor device capable of preventing malfunction of a Schottky diode to reduce a failure ratio of the semiconductor device and a method for fabricating the same are disclosed. The semiconductor device includes first and second CMOS switching devices formed over a silicon substrate, a Schottky diode formed in a Schottky diode region, and a Schottky diode isolation film surrounding the Schottky diode region and isolating the Schottky diode from the silicon substrate.
1. A method comprising:
forming first and second CMOS switching devices over a silicon substrate;
forming a Schottky diode isolation film to surround a Schottky diode region to isolate the Schottky diode from the silicon substrate; and
forming a Schottky diode substantially simultaneously with said forming the first and second CMOS switching devices.
2. The method of claim 1 , wherein said forming the Schottky diode isolation film includes:
forming an impurity diffusion region to surround a lower surface of the Schottky diode region; and
forming an impurity isolation region to surround a side surface of the Schottky diode region.
3. The method of claim 2 , wherein the step of forming a Schottky diode isolation film further includes:
forming a silicide film over the impurity isolation region; and
forming a connection terminal, serving as a metal line, over the silicide film.
4. The method of claim 3 , wherein the step of forming a Schottky diode isolation film further includes applying a ground voltage to the connection terminal and the silicide film.
5. The method of claim 3 , wherein a Schottky barrier metal is deposited over the silicide film and patterned.
6. The method of claim 5 , wherein the Schottky barrier metal is a TiW film.
7. The method of claim 3 , wherein the connection terminal is formed from aluminum.
8. The method of claim 2 , wherein the impurity diffusion region is formed to be larger than the Schottky diode region.
9. The method of claim 2 , wherein the impurity isolation region is connected to the impurity diffusion region.
10. The method of claim 2 , wherein a first and a second parasitic diode are formed in the Schottky diode region.
11. The method of claim 10 , wherein the first and second parasitic diodes are oriented opposite each other.
12. The method of claim 11 , wherein the first parasitic diode prevents operation of the second parasitic diode, and the second parasitic diode prevents operation of the first parasitic diode.
13. The method of claim 1 , wherein a single ion implantation process forms a lightly doped impurity region in the first CMOS switching device at opposite sides of a first gate electrode and a first lightly doped drain in a cathode formation region of the Schottky diode.
14. The method of claim 13 , wherein a single ion implantation process forms a lightly doped drain region in the second CMOS switching device at opposite sides of a second gate electrode and a first lightly doped impurity in an anode formation region of the Schottky diode.
15. The method of claim 1 , wherein a shallow trench isolation process is used to form the Schottky diode isolation film.
16. The method of claim 1 , wherein a local oxidation of silicon process is used to form the Schottky diode isolation film.