Semiconductor device and method for fabricating the same
View Patent ↗A non-volatile memory semiconductor device and a method for fabricating the same are disclosed. The semiconductor device includes a PN junction diode formed over a semiconductor substrate. Insulating films may be formed over the PN junction diode and patterned to have via holes. A resistive random access memory including a first metal pattern may be in contact with a first region of the PN junction diode. An oxide film pattern may be formed over the first metal pattern and a second metal pattern formed over the oxide film pattern. The first metal pattern, the oxide film pattern and the second metal pattern may be formed in the via holes.
1. An apparatus comprising:
a PN junction diode formed over a semiconductor substrate;
insulating films formed over the PN junction diode and patterned to have via holes; and
a resistive random access memory including a first metal pattern in contact with a first region of the PN junction diode, an oxide film pattern formed over the first metal pattern and a second metal pattern formed over the oxide film pattern, wherein the first metal pattern, the oxide film pattern and the second metal pattern are formed in the via holes.
2. The apparatus of claim 1 , wherein the resistive random access memory comprises:
a first metal line connected to a second region of the PN junction diode; and
a second metal line connected to the second metal pattern.
3. The apparatus of claim 1 , wherein the PN junction diode comprises:
a first impurity region formed by implanting first impurities in the semiconductor substrate; and
a second impurity region formed by implanting second impurities into a portion of the first impurity region.
4. The apparatus of claim 2 , wherein the PN junction diode includes:
a first impurity region formed by implanting first impurities into the semiconductor substrate; and
a second impurity region formed by implanting second impurities into a portion of the first impurity region.
5. The apparatus of claim 4 , wherein the first impurities are n-type impurities and the second impurities are p-type impurities.
6. The apparatus of claim 5 , wherein the first metal pattern is in contact with the second impurity region and the first metal line is connected to the first impurity region.
7. The apparatus of claim 1 , wherein the insulating films include:
a first insulating film having a first via hole and the first metal pattern formed in the first via hole;
a second insulating film formed over the first insulating film and having a second via hole and the oxide film pattern formed in the second via hole; and
a third insulating film formed over the second insulating film and having a third via hole and the second metal pattern formed in the third via hole.
8. The apparatus of claim 6 , wherein the insulating films includes:
a first insulating film having a first via hole, a fourth via hole, the first metal pattern formed in the first via hole and a third metal pattern formed in the fourth via hole;
a second insulating film formed over the first insulating film and having a second via hole and the oxide film pattern formed in the second via hole; and
a third insulating film formed over the second insulating film and having a third via hole and the second metal pattern formed in the third via hole.
9. The apparatus of claim 8 , wherein the first via hole, the second via hole, and the third via hole are arranged in a vertical line.
10. The apparatus of claim 8 , wherein the first metal pattern is in contact with the second impurity region and the third metal pattern is in contact with the first impurity region.
11. The apparatus of claim 1 , wherein the first metal pattern comprises at least one of Ni, Zr, Pt, Au, Al, Cu, and Ti.
12. The apparatus of claim 1 , wherein the second metal pattern comprises at least one of Ni, Zr, Pt, Au, Al, Cu and, Ti.
13. A method comprising:
forming a first impurity region by implanting first impurities into a semiconductor substrate;
forming a second impurity region by implanting second impurities into the first impurity region;
forming a first insulating film over the semiconductor substrate and forming a first via hole in the first insulating film to expose a portion of the second impurity region;
forming a first metal pattern in the first via hole by depositing a metal film over the first insulating film and polishing the metal film;
forming a second insulating film over the first insulating film and forming a second via hole in the second insulating film to expose the first metal pattern;
forming an oxide film pattern in the second via hole by depositing an oxide film over the second insulating film and polishing the oxide film;
forming a third insulating film over the second insulating film and forming a third via hole in the third insulating film to expose the oxide film pattern; and
forming a second metal pattern in the third via hole by depositing a metal film over the third insulating film and polishing the metal film.
14. The method of claim 13 , comprising forming a fourth via hole in the first insulating film to expose a portion of the first impurity region and forming a third metal pattern in the fourth via hole.
15. The method of claim 14 , comprising forming a first metal line, connected to the third metal pattern, over the first insulating film.
16. The method of claim 13 , comprising forming a second metal line, connected to the second metal pattern, over the third insulating film.
17. The method of claim 13 , wherein the first impurities are p-type impurities and the second impurities are n-type impurities.
18. The method of claim 13 , comprising planarizing the second insulating film after forming the second insulating film.
19. The method of claim 13 , wherein the first metal pattern comprises at least one of Ni, Zr, Pt, Au, Al, Cu, and Ti.
20. The method of claim 13 , wherein the second metal pattern comprises at least one of Ni, Zr, Pt, Au, Al, Cu, and Ti.