Phase change memory element and method for forming the same

1. A phase change memory element, comprising;

a substrate;

a plurality of rectangle-shaped dielectric patterns formed on the substrate and parallel with each other;

a plurality of electric conductive patterns partially covering a first sidewall and the top surface of the rectangle-shaped dielectric pattern and the substrate to expose a part of the first sidewall and a second sidewall of the rectangle-shaped dielectric pattern, wherein the electric conductive patterns covering the same rectangle-shaped dielectric pattern are apart from each other;

a phase change spacer formed on the substrate and directly in contact with the exposed first and second sidewalls of the rectangle-shaped dielectric patterns, wherein the two adjacent electric conductive patterns covering the same rectangle-shaped dielectric pattern are electrically connected by the phase change spacer; and

a dielectric layer formed on the substrate, wherein a contact hole passes through the dielectric layer exposing the top surface of the patterned electric conductive layer.

2. The phase change memory element as claimed in claim 1 , wherein the rectangle-shaped dielectric pattern comprises a silicon-containing layer.

3. The phase change memory element as claimed in claim 1 , wherein the rectangle-shaped dielectric patterns are apart from each other by a specific distance.

4. The phase change memory element as claimed in claim 1 , wherein the electric conductive pattern comprises Pt, Au, Ag, Pd, Ru, RuO, Ir, IrO, TiN, TiAlN, TaN, or combinations thereof.

5. The phase change memory element as claimed in claim 1 , wherein the electric conductive patterns are rectangle-shaped, and wherein the extended direction of the rectangle-shaped dielectric patterns is perpendicular to that of the rectangle-shaped electric conductive patterns.

6. The phase change memory element as claimed in claim 1 , wherein the phase change spacer comprises chalcogenide.

7. The phase change memory element as claimed in claim 1 , wherein the profile dimension of the phase change spacer is less than the resolution limit of photolithography process.

8. The phase change memory element as claimed in claim 1 , wherein the first sidewall of the rectangle-shaped dielectric pattern is alternately covered by the electric conductive patterns and the phase change spacer.

9. The phase change memory element as claimed in claim 1 , wherein the electric conductive pattern is electrically contacted to a metal-oxide-semiconductor.

10. A method for forming a phase change memory element, comprising:

providing a substrate;

forming a plurality of parallel rectangle-shaped dielectric patterns on the substrate;

conformally forming an electric conductive layer on the substrate, completely covering a first and second sidewalls and the top surface of the rectangle-shaped dielectric pattern;

patterning the electric conductive layer to form a plurality of electric conductive patterns, wherein the electric conductive patterns partially covers the first sidewall and the top surface of the rectangle-shaped dielectric pattern and the substrate, exposing a part of the first sidewall and the whole second sidewall, wherein the electric conductive patterns covering the same rectangle-shaped dielectric pattern are apart from each other;

conformally forming a phase change layer on the substrate to cover the exposed first and second sidewalls and the top surface of the rectangle-shaped dielectric patterns;

anisotropically etching the phase change layer to form a phase change spacer on the substrate, wherein the phase change spacer directly contacts the exposed first sidewall of the rectangle-shaped dielectric patterns, and wherein the two adjacent electric conductive patterns covering the same rectangle-shaped dielectric pattern are electrically connected by the phase change spacer;

forming a dielectric layer on the substrate; and

etching the dielectric layer to form a contact hole passing through the dielectric layer to expose the top surface of the electric conductive patterns.

11. The method as claimed in claim 10 , wherein the rectangle-shaped dielectric pattern comprises a silicon-containing layer.

12. The method as claimed in claim 10 , wherein the rectangle-shaped dielectric patterns are apart from each other by a specific distance.

13. The method as claimed in claim 10 , wherein the electric conductive pattern comprises Pt, Au, Ag, Pd, Ru, RuO, Ir, IrO, TiN, TiAlN, TaN, or combinations thereof.

14. The method as claimed in claim 10 , wherein the electric conductive patterns are rectangle-shaped, wherein the extended direction of the rectangle-shaped dielectric patterns is perpendicular to that of the rectangle-shaped electric conductive patterns.

15. The method as claimed in claim 10 , wherein the phase change spacer comprises chalcogenide.

16. The method as claimed in claim 10 , wherein the profile dimension of the phase change spacer is less than the resolution limit of photolithography process.

17. The method as claimed in claim 10 , wherein the first sidewall of the rectangle-shaped dielectric pattern is alternately covered by the electric conductive patterns and the phase change spacer.

18. The method as claimed in claim 10 , wherein the anisotropic etching process comprises a dry etching process.

19. The method as claimed in claim 10 , wherein a part of surface of the substrate is exposed after forming the plurality of parallel rectangle-shaped dielectric patterns on the substrate.