MIM capacitor and method of fabricating the same
View Patent ↗A M-I-M capacitor semiconductor device capable of enhancing the reliability and capacitance of a capacitor and maximizing the integration density of the device, and a method of fabricating the same are disclosed. The semiconductor device includes a semiconductor substrate, a capacitor lower metal layer formed over the semiconductor substrate, a SiN capacitor dielectric layer having a thickness of approximately 30 nm or less formed over the capacitor lower metal layer, and a capacitor upper metal layer formed over a portion of the capacitor dielectric layer and overlapping with the capacitor lower metal layer.
1. A method comprising:
forming a capacitor lower metal layer over a semiconductor substrate including a plurality of layers;
forming a SiN layer over the capacitor lower metal layer;
reacting a surface of the SiN layer with a mixture of Ar gas and at least one of NF 3 and NH 3 gas via a remote plasma process to form a capacitor dielectric layer having a thickness of approximately 30 nm or less;
forming a capacitor upper metal layer over the capacitor dielectric layer,
forming a second insulating layer to cover a metal-insulator-metal capacitor region including the capacitor lower metal layer, the capacitor dielectric layer, and the capacitor upper metal layer;
forming an fluorine doped silicate glass layer, a third D-TEOS insulating layer, a SiN layer, and a fourth D-TEOS insulating layer sequentially over the entire surface of the semiconductor substrate;
forming a first contact layer by a conductive material and penetrating through the second and third insulating layers, to electrically connect the first bonding metal layer and the capacitor upper metal layer to each other;
forming a second contact layer by a conductive material and penetrating through the second and third insulating layers and the capacitor dielectric layer, to electrically connect the second bonding metal layer and the capacitor lower metal layer to each other,
wherein first and second bonding metal layers formed of conductive metals and penetrating through the fourth insulating layer and the SiN layer.
2. The method of claim 1 , wherein the surface of the SiN layer is subjected to the remote plasma process using an RF power of approximately 100 W to 400 W.
3. The method of claim 2 , wherein the surface of the SiN layer is subjected to the remote plasma process using a mixture of at least one of NF 3 and NH 3 gas at approximately 1,000 sccm to 3,000 sccm.
4. The method of claim 3 , wherein the surface of the SiN layer is subjected to the remote plasma process using Ar gas at approximately 500 sccm to 3,000 sccm.
5. The method of claim 4 , wherein the surface of the SiN layer is subjected to the remote plasma process using a pressure of approximately 4 Torr to 30 Torr.
6. The method of claim 1 , wherein the semiconductor substrate includes at least one of a fluorine doped silicate glass layer, a SiH 4 oxide layer, and a SiN layer.
7. The method of claim 1 , wherein each of the capacitor lower metal layer and the capacitor upper metal layer is formed of at least one Ti and one TiN layer.
8. The method of claim 7 , wherein the Ti layer has a thickness of approximately 1,000 Å to 1,600 Å.
9. The method of claim 7 , wherein the TiN layer has a thickness of approximately 200 Å to 800 Å.
10. An apparatus comprising:
a semiconductor substrate;
a capacitor lower metal layer formed over the semiconductor substrate;
a SiN capacitor dielectric layer having a thickness of approximately 30 nm or less formed over the capacitor lower metal layer;
a capacitor upper metal layer formed over a portion of the capacitor dielectric layer and overlapping with the capacitor lower metal layer,
a second insulating layer formed to cover a metal-insulator-metal capacitor region including the capacitor lower metal laver, the capacitor dielectric layer, and the capacitor upper metal layer; and
an fluorine doped silicate glass layer, a third D-TEOS insulating layer, a SiN layer, and a fourth D-TEOS insulating layer sequentially formed over the entire surface of the semiconductor substrate.
11. The apparatus of claim 10 , wherein the capacitor dielectric layer is formed via a remote plasma reaction between a SiN layer surface and a mixture of NF 3 gas and argon gas.
12. The apparatus of claim 10 , wherein the capacitor dielectric layer is formed via a remote plasma reaction between a SiN layer surface and a mixture of NH 3 gas and argon gas.
13. The apparatus of claim 10 , wherein the semiconductor substrate includes at least one of a fluorine doped silicate glass layer, a first SiH 4 oxide insulating layer, and a SiN layer.
14. The apparatus of claim 10 , wherein each of the capacitor lower metal layer and the capacitor upper metal layer is formed of at least one Ti and one TiN layer.
15. The apparatus of claim 14 , wherein the Ti layer has a thickness of approximately 1,000 Å to 1,600 Å.
16. The apparatus of claim 14 , wherein the TiN layer has a thickness of approximately 200 Å to 800 Å.
17. The apparatus of claim 10 , comprising:
first and second bonding metal layers formed of conductive metals and penetrating through the fourth insulating layer and the SiN layer.
18. The apparatus of claim 17 , comprising:
a first contact layer formed of a conductive material and penetrating through the second and third insulating layers, to electrically connect the first bonding metal layer and the capacitor upper metal layer to each other.
19. The apparatus of claim 18 , comprising:
a second contact layer formed of a conductive material and penetrating through the second and third insulating layers and the capacitor dielectric layer, to electrically connect the second bonding metal layer and the capacitor lower metal layer to each other.