IP Library Granted Patent US 7,999,292
Granted Patent B2
US 7,999,292 · App. 12/204,848 · Granted Aug 16, 2011

Image sensor and manufacturing method thereof

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Quick Facts
Patent No.
US 7,999,292
App. No.
12/204,848
Granted
Aug 16, 2011
Kind
B2
Abstract

An image sensor can be formed of a first substrate having a readout circuitry, an interlayer dielectric, and lower lines, and a second substrate having a photodiode. The first substrate comprises a pixel portion and a peripheral portion. The readout circuitry is formed on the pixel portion. The interlayer dielectric is formed on the pixel portion and the peripheral portion. The lower lines pass through the interlayer dielectric to electrically connect with the readout circuitry and the peripheral portion. The photodiode is bonded to the first substrate and etched to correspond to the pixel portion. A transparent electrode is formed on the interlayer dielectric on which the photodiode is formed such that the transparent electrode can be connected with the photodiode and the lower line in the peripheral portion. A first passivation layer can be formed on the transparent electrode. In one embodiment, the first passivation layer includes a trench exposing a portion of the transparent electrode. Then, an upper line can be formed on the peripheral portion and in the trench to shield a lateral side of the photodiode.

Claims (54)

1. An image sensor comprising:

a first substrate comprising a pixel portion and a peripheral portion;

a readout circuitry on the pixel portion;

an interlayer dielectric on the first substrate, including on the pixel portion and the peripheral portion;

a first lower line passing through the interlayer dielectric to electrically connect with the readout circuitry;

a second lower line passing through the interlayer dielectric to electrically connect with the peripheral portion;

a photodiode on a portion of the interlayer dielectric corresponding to the pixel portion;

a transparent electrode on the interlayer dielectric on which the photodiode is formed, the transparent electrode being electrically connected with the photodiode and the second lower line of the peripheral portion;

a first passivation layer on the transparent electrode, the first passivation layer comprising a trench exposing a portion of the transparent electrode; and

an upper line on the peripheral portion, including in the trench of the first passivation layer, wherein the upper line shields a side of the photodiode at an edge of the pixel portion.

2. The image sensor according to claim 1 , further comprising:

a second passivation layer on the first passivation layer and the upper line; and

a color filter on a portion of the second passivation layer corresponding to the photodiode.

3. The image sensor according to claim 1 , wherein the readout circuitry comprises an electrical junction region in the first substrate, wherein the electrical junction region comprises:

a first conduction type ion implantation region in the first substrate; and

a second conduction type ion implantation region on the first conduction type ion implantation region.

4. The image sensor according to claim 3 , further comprising a first conduction type connection region electrically connected with the first lower line on the electrical junction region.

5. The image sensor according to claim 3 , further comprising a first conduction type connection region electrically connected with the first lower line at a side of the electrical junction region.

6. The image sensor according to claim 1 , wherein the readout circuitry is designed such that there is a potential difference between a source and a drain of a transistor, wherein the source of the transistor is electrically connected to the first lower line.

7. The image sensor according to claim 6 , wherein the transistor comprises a transfer transistor, and wherein an ion implantation concentration of the source of the transfer transistor is lower than an ion implantation concentration of a floating diffusion region at the drain of the transfer transistor.

8. The image sensor according to claim 1 , wherein the transparent electrode is formed on only the pixel portion, wherein the first passivation layer is provided on the transparent electrode and the peripheral portion, wherein the first passivation layer further comprises a second trench exposing the second lower line wherein the trench exposing a portion of the transparent electrode is provided corresponding to an edge region of the photodiode, and wherein the upper line extends from the first trench to the second trench and is formed on a portion of the first passivation layer corresponding to a lateral side of the photodiode.

9. The image sensor according to claim 1 , wherein the trench is provided on the peripheral portion, wherein a top surface of the upper line has a same height as a top surface of the first passivation layer on the pixel portion.

10. A method for manufacturing an image sensor, the method comprising:

preparing a first substrate where a pixel portion and a peripheral portion are defined;

forming a readout circuitry on the pixel portion;

forming an interlayer dielectric on the first substrate including the pixel portion and the peripheral portion;

forming a first lower line connected with the readout circuitry and a second lower line connected with the peripheral portion, in the interlayer dielectric;

preparing a second substrate comprising a crystalline semiconductor layer;

forming a photodiode in the crystalline semiconductor layer;

bonding the first substrate and the second substrate such that the first lower line of the first substrate is electrically connected with the photodiode;

separating the second substrate to expose the photodiode on the first substrate;

removing a portion of the photodiode corresponding to the peripheral portion, such that the photodiode remains only on the pixel portion, to expose the second lower line on the peripheral portion;

forming a transparent electrode layer on the first substrate on which the photodiode is provided;

forming a first passivation layer on the transparent electrode layer;

forming a first trench in a portion of the first passivation layer to expose a portion of the transparent electrode layer; and

forming an upper line on the peripheral portion including in the first trench.

11. The method according to claim 10 , wherein the transparent electrode layer is connected with the photodiode and the second lower line; wherein the first trench exposes the portion of the transparent electrode layer corresponding to a region on the peripheral portion; wherein the forming of the upper line comprises:

forming a metal layer on the first passivation layer comprising the trench; and

planarizing the metal layer such that the metal layer has the same height as a top surface of the first passivation layer of the pixel portion.

12. The method according to claim 10 , wherein forming the transparent electrode layer comprises:

depositing transparent electrode material on the first substrate; and

removing a portion of the transparent electrode material corresponding to the peripheral portion, the method further comprising:

forming a second trench in the first passivation layer, wherein the second trench exposes a top surface of the second lower line, wherein the first trench is formed to expose the portion of the transparent electrode layer at an edge of the pixel portion.

13. The method according to claim 12 , wherein forming the upper line on the peripheral portion including in the first trench comprises:

forming the upper line in the first trench and the second trench such that the upper line extends from the first trench to the second trench including on a portion of the first passivation layer corresponding to a lateral side of the photodiode.

14. The method according to claim 10 , further comprising, after the forming of the upper line:

forming a second passivation layer on the first passivation layer and the upper line; and

forming a color filter on a portion of the second passivation layer corresponding to the photodiode.

15. The method according to claim 10 , wherein the forming of the readout circuitry comprises forming an electrical junction region in the first substrate, wherein the forming of the electrical junction region in the first substrate comprises:

forming a first conduction type ion implantation region in the first substrate; and

forming a second conduction type ion implantation region on the first conduction type ion implantation region.

16. The method according to claim 15 , further comprising forming a first conduction type connection region connected with the first line on the electrical junction region.

17. The method according to claim 16 , wherein the forming of the first conduction type connection region is performed after a contact etch for the first lower line.

18. The method according to claim 15 , further comprising forming a first conduction type connection region connected with the first line at a side of the electrical junction region.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2017
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 041343/0241 →
CORRECTIVE ASSIGNMENT TO CORRECT REMOVE PATENT NO. 878209 FROM EXHIBIT B PREVIOUSLY RECORDED AT REEL: 034009 FRAME: 0157. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 24, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034087/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034009/0157 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2008
From: HWANG, JOON
To: DONGBU HITEK CO., LTD.
Reel/Frame 021493/0823 →